Non-volatile Memory Plane Independent Screening

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Solution Overview

Problem

Prior art systems in non-volatile storage often retire healthy memory blocks along with defective ones, reducing storage capacity due to inadequate identification of defective blocks during programming, and require all planes to complete a data state before progressing, leading to inefficiencies.

Innovation Solution

Implementing a system where the completion of programming in a fastest plane serves as a trigger to test for program failure in other planes, allowing independent verification and preventing retirement of healthy blocks, thus optimizing storage capacity and efficiency.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If all planes must complete a data state before the system progresses, then programming reliability is maintained, but system productivity decreases due to waiting for slower planes

Engineering Contradiction:
Improveprogramming reliabilityVSAvoidsystem productivity
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent segments the verification process by plane, allowing each plane to be verified independently rather than requiring all planes to complete together. The control circuit determines program failure for each plane separately based on its own verification results, enabling parallel processing and eliminating the bottleneck caused by waiting for slower planes.

Inventive Principle:
Principle #1Segmentation

2Reliability

If defective blocks are identified during programming, then storage reliability improves, but healthy blocks may be incorrectly retired along with defective ones, reducing storage capacity

Engineering Contradiction:
Improvestorage reliabilityVSAvoidstorage capacity
Core Design Contradiction:
ReliabilityVSQuantity of substance

Solution Approach 1:

The patent extracts the verification and failure determination process from a collective plane-level operation to an independent block-level operation. By determining program failure separately for each plane based on individual verification results, the system can identify and retire only the specific defective blocks while preserving healthy blocks that would otherwise be incorrectly retired.

Inventive Principle:
Principle #2Taking out (Extraction)

3Measurement precision

If the system waits for all planes to complete programming before verification, then measurement precision is ensured, but loss of time increases

Engineering Contradiction:
Improveverification accuracyVSAvoidprogramming time
Core Design Contradiction:
Measurement precisionVSLoss of time

Solution Approach 1:

The patent implements preliminary verification during the programming process itself. Rather than waiting for all planes to complete before verifying any, the system performs verification for each plane as soon as its programming is complete, using the completion of one plane as a trigger to initiate verification for that plane while other planes continue programming. This overlapping execution reduces total time while maintaining accuracy.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS11862256B2Non-volatile memory with plane independent screening
Publication Date: 2024.01.02 SANDISK TECHNOLOGIES LLC
  • US11862256B2 patent drawing
  • US11862256B2 patent drawing
  • US11862256B2 patent drawing

AI summary

A non-volatile storage apparatus that comprises a plurality of planes of non-volatile memory cells is capable of concurrently programming memory cells in multiple planes. In order to screen for failure of the programming process in a subset of planes, the completion of programming of a fastest plane to a particular data state is used as a trigger to test for program failure of other planes to a different data state. In one embodiment, the test for program failure of other planes to the different data state comprises determining if the memory cells of the other planes that are targeted for programming to the different data state have successfully completed verification of programming for the different data state. The programming process is stopped for those planes that fail the test.