Non-Volatile Memory Plasma Charge Protection via Junction Diode
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Solution Overview
Problem
Non-volatile memory devices are susceptible to damage and degradation due to local charge irregularities caused by plasma charges during manufacturing processes involving plasma phenomena, such as deposition and etching.
Innovation Solution
Incorporation of a junction diode in the semiconductor device structure to disperse electric charges generated during the plasma process, connecting metal lines and contact plugs through interlayer insulation films, allowing plasma charges to be directed away from critical components like the gate insulation film.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If plasma processes (etching, deposition) are used in manufacturing, then film deposition and pattern formation are achieved, but local charge irregularities cause gate insulation film damage and film quality degradation
Solution Approach 1:
A separate well region (first well region) is introduced as an intermediary structure to receive and isolate plasma charges, preventing them from reaching the gate insulation film. This mediator well acts as a charge sink that protects the critical gate insulation film from plasma-induced damage while allowing plasma processes to continue in the source/drain regions.
Solution Approach 2:
The semiconductor substrate is segmented into distinct functional regions: a second well region for the junction, a first well region specifically for receiving plasma charges, and the gate electrode structure. This segmentation allows plasma charges to be confined to a specific region (first well) separate from the gate insulation film, preventing charge accumulation damage.
2Productivity
If plasma processes are used for deposition and etching, then device fabrication is enabled, but film quality degrades due to charge irregularity
Solution Approach 1:
The first well region serves as a mediator that intercepts plasma charges before they can affect the film quality in critical regions. By providing a dedicated charge collection zone, the film deposition and etching processes can proceed with maintained quality, as charges are funneled to the well rather than accumulating irregularly in the film layers.
3Device complexity
If conventional structure without separate charge reception well is used, then device complexity is reduced, but plasma charge damage occurs
Solution Approach 1:
The harmful plasma charges are converted into a manageable phenomenon by directing them to the first well region, where they are safely collected. The well acts as a designated zone that transforms the harmful charge accumulation problem into a controlled charge reception process, protecting the gate insulation film while maintaining overall structural efficiency.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Prevents damage to the semiconductor device by effectively dispersing plasma charges, thereby maintaining film quality and device integrity.
Implementation Method 1
a variety of processes employing a plasma phenomenon have been used. For example, the processes may include deposition of an insulation film or a metal film using plasma etch and plasma. Plasma is a light gas having electric charges.
Implementation Method 2
a junction diode in which the second metal line, the second contact plug, the first metal line, the first contact plug, the third metal line, the fourth contact plug, the third contact plug, and the junction region are interconnected
Data Source
AI summary
A non-volatile memory device for preventing damage by plasma charges includes a gate electrode formed on a predetermined region of a semiconductor substrate, a source/drain region which is overlapped with the gate electrode and formed in a first well region of the semiconductor substrate, a first metal line coupled to the gate electrode through a first contact plug, a second metal line coupled to the first metal line through a second contact plug so that an external voltage is transferred to the gate electrode, a junction region formed in a second well region separated from the first well region, and a third metal line coupled to the junction region through a third contact plug and coupled to the second metal line through a fourth contact plug.