Nonvolatile Memory Point-to-Point Channels

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Typical nonvolatile memory systems face signal integrity issues due to shared bus communication, which degrade as the number of connected elements increases, leading to reduced bandwidth and increased latency.

Innovation Solution

Implementing point-to-point communication channels using switches like multiplexers throughout the system, allowing memory controllers to adjust the number of active external interfaces based on host and interface speeds, and utilizing power islands to optimize communication and reduce power consumption.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If a shared bus communication system is used to connect multiple memory controllers and memory dies, then the system can support multiple elements, but signal integrity deteriorates as the number of connected elements increases

Engineering Contradiction:
Improvenumber of connected elementsVSAvoidsignal integrity
Core Design Contradiction:
Adaptability or versatilityVSReliability

Solution Approach 1:

The shared bus communication system is segmented into multiple point-to-point communication channels. Each memory controller is connected to memory dies through dedicated communication paths rather than a common shared bus, dividing the communication load and isolating signal interference between different channels.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Switches are introduced as intermediary devices between memory controllers and memory dies. These switches dynamically route communication signals through selected point-to-point channels, enabling flexible connectivity while maintaining signal integrity by avoiding direct shared bus connections.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Productivity

If the number of active external interfaces is increased to improve communication capacity, then bandwidth increases, but power consumption increases

Engineering Contradiction:
ImprovebandwidthVSAvoidpower consumption
Core Design Contradiction:
ProductivityVSUse of energy by moving object

Solution Approach 1:

The system dynamically adjusts the number of active external interfaces based on real-time communication demands. Memory controllers can activate or deactivate interfaces as needed, allowing bandwidth to scale with workload while minimizing power consumption during low-activity periods.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The system changes operational parameters by adjusting the number of active communication interfaces according to system workload. This allows the communication capacity to be optimized for performance when needed while reducing power consumption during normal operation.

Inventive Principle:
Principle #35Parameter changes

3Reliability

If switches are used to toggle between multiple communication channels for point-to-point communication, then signal integrity is improved, but device complexity increases

Engineering Contradiction:
Improvesignal integrityVSAvoidnumber of switches and channels
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The switches implemented in the system are multi-functional devices that can route communication signals between multiple memory controllers and multiple memory dies. Each switch serves as a universal routing element that can establish point-to-point connections dynamically, reducing the need for dedicated routing hardware for each connection.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS9164680B2Systems and methods for improved communications in a nonvolatile memory system
Publication Date: 2015.10.20 APPLE INC
  • US9164680B2 patent drawing
  • US9164680B2 patent drawing
  • US9164680B2 patent drawing

AI summary

Systems and methods are provided for improved communications in a nonvolatile memory (“NVM”) system. The system can toggle between multiple communications channels to provide point-to-point communications between a host device and NVM dies included in the system. The host device can toggle between multiple communications channels that extend to one or more memory controllers of the system, and the memory controllers can toggle between multiple communications channels that extend to the NVM dies. Power islands may be incorporated into the system to electrically isolate system components associated with inactive communications channels.