Non-volatile Memory Program Method for Parasitic Capacitance
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Solution Overview
Problem
The increased chip layout density in non-volatile memory devices leads to reduced programming speed due to parasitic capacitance among word lines, which slows down voltage adjustment and operating efficiency.
Innovation Solution
A program method for non-volatile memory that involves setting one word line as a program word line and raising its voltage from a reference to a first program voltage during a first sub-time period, then to a second, higher voltage during a second sub-time period, while simultaneously raising unselected word lines to a pass voltage, thereby reducing the parasitic capacitance effect and accelerating programming.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If chip layout density is increased to provide larger capacity, then memory capacity is improved, but parasitic capacitance among word lines increases which slows down voltage adjustment speed
Solution Approach 1:
The patent segments the programming process into multiple stages with different voltage levels. The program word line voltage is divided into a first program voltage (lower) and a second program voltage (higher), applied in sequence rather than immediately applying the full high voltage. This segmentation allows the system to overcome the parasitic capacitance barrier gradually, enabling faster voltage adjustment despite high chip density.
2Reliability
If voltage on program word line is raised to high voltage value to complete programming, then programming capability is improved, but parasitic capacitance among word lines causes slower voltage rise
Solution Approach 1:
The patent applies a preliminary lower voltage (first program voltage) to the program word line before applying the full high voltage (second program voltage). This preliminary action partially charges the parasitic capacitance in advance, reducing the charge required to reach the final high voltage state. Additionally, unselected word lines are pre-charged to a pass voltage, further reducing the parasitic capacitance burden during the final voltage surge, thereby accelerating the voltage rise speed while maintaining programming capability.
3Speed
If voltage on unselected word lines is raised to pass voltage during second sub-time period, then parasitic capacitance effect is reduced, but programming time is divided into multiple sub-time periods
Solution Approach 1:
The patent employs periodic action by dividing the programming operation into distinct time periods (first sub-time period and second sub-time period) with specific voltage application patterns. During the first sub-time period, the program word line receives the first program voltage. During the second sub-time period, both the program word line voltage is increased to the second program voltage and unselected word lines are raised to pass voltage. This periodic, staged approach optimizes the balance between reducing parasitic capacitance effects and maintaining a structured, manageable programming time sequence.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method effectively reduces the time required for programming by rapidly raising the voltage on the program word line to a sufficient level, enhancing the operating efficiency of non-volatile memory cells.
Implementation Method 1
the voltage adjustment of the word lines is considerably influenced by the parasitic capacitance among the word lines
Data Source
AI summary
A non-volatile memory and a program method thereof are provided. The program method includes: setting one of a plurality of word lines to be a program word line, setting the word lines except the program word line to be a plurality of unselected word lines; raise a voltage on the program word line from a reference voltage to a first program voltage during a first sub-time period of a program time period; raising the voltage on the program word line from the first program voltage to a second program voltage during a second sub-time period of the program time period; and raising voltages on at least part of the unselected word lines from the reference voltage to a pass voltage during the second sub-time period.