Non-Volatile Memory Programming Speed Compaction
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Solution Overview
Problem
As memory devices scale down, the natural threshold voltage distribution of storage elements in non-volatile memory systems widens, leading to increased programming time due to the need for more verify operations, which degrades performance.
Innovation Solution
A multi-phase programming method is employed where faster-programming storage elements are identified and slowed down using a raised bit line voltage, tightening the natural threshold voltage distribution and reducing the number of verify operations required.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If memory devices are scaled down, then memory size is reduced, but the natural threshold voltage distribution widens leading to increased programming time
Solution Approach 1:
The programming operation is divided into multiple phases: a first programming phase that programs storage elements to a first data state, and a second programming phase that programs storage elements to a second data state. This segmentation allows the system to manage the widened threshold voltage distribution by handling different data states in separate phases, thereby reducing the overall programming time despite memory scaling.
Solution Approach 2:
The first programming phase is performed before the second programming phase. By preliminarily programming storage elements to the first data state, the system prepares the threshold voltage distribution in advance, which facilitates the subsequent second programming phase and reduces the total programming time required for scaled-down memory devices.
2Manufacturing precision
If the natural threshold voltage distribution is widened, then more verify operations are required, but this increases programming time and degrades performance
Solution Approach 1:
The programming operation is divided into multiple phases: a first programming phase that programs storage elements to a first data state, and a second programming phase that programs storage elements to a second data state. This segmentation allows the system to manage the widened threshold voltage distribution by handling different data states in separate phases, thereby reducing the overall programming time despite memory scaling.
Solution Approach 2:
The patent employs periodic programming and verifying operations in alternating cycles. Program pulses are applied to programming storage elements, followed by verify operations to detect programmed storage elements. This periodic action allows the system to systematically manage the widened threshold voltage distribution through repeated programming-verify cycles, improving programming performance by efficiently identifying and handling programmed elements across multiple periods.
Data Source
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AI summary
In a non-volatile memory system, a programming speed-based slow down measure such as a raised bit line is applied to the faster-programming storage elements. A multi-phase programming operation which uses a back- and-forth word line order is performed in which programming speed data is stored in latches in one programming phase and read from the latches for use in a subsequent programming phase of a given word line. The faster and slower- programming storage elements can be distinguished by detecting when a number of storage elements reach a specified verify level, counting an additional number of program pulses which is set based on a natural threshold voltage distribution of the storage elements, and subsequently performing a read operation that separates the faster and slower programming storage elements. A drain-side select gate voltage can be adjusted in different programming phases to accommodate different bit line bias levels.