Multi-Level Non-Volatile Memory Programming Speed via Verify Reduction
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Solution Overview
Problem
Current non-volatile memory programming techniques face challenges in achieving high programming speeds due to the need for multiple verify operations, which can slow down the process and increase programming time, especially for multi-level storage devices.
Innovation Solution
The method involves optimizing verify operations by reducing the number of verify operations for certain states, particularly by performing fewer verify operations for higher states and adjusting the frequency of verify operations based on the programming progress, allowing for faster programming pulses and reduced overall programming time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If multiple verify operations are performed for each state of multi-level memory elements, then programming accuracy is improved, but programming speed deteriorates
Solution Approach 1:
The patent applies partial verify operations by performing fewer verify operations for higher states compared to lower states. Specifically, for a 4-level memory device with states S0-S3, the patent performs 3 verify operations for S0, 2 for S1, 1 for S2, and 0 for S3 during certain programming phases. This partial action approach maintains sufficient programming accuracy while reducing the total number of verify operations to accelerate programming speed.
Solution Approach 2:
The patent dynamically adjusts the number of verify operations based on the programming phase and target state. During initial programming phases, fewer verify operations are performed for higher states, while more verify operations are performed later in the programming process when needed. This dynamic adjustment optimizes the balance between programming speed and accuracy throughout the programming sequence.
2Manufacturing precision
If verify operations are performed after each programming pulse, then threshold voltage control precision is improved, but programming time increases
Solution Approach 1:
The patent implements periodic verify operations where verify operations are performed after certain programming pulses rather than after every single pulse. The verify operations occur periodically at strategically selected intervals during the programming sequence, maintaining threshold voltage control precision while reducing the frequency of verify operations to minimize programming time.
Solution Approach 2:
The patent performs verify operations at predetermined points in the programming sequence based on pre-planned programming phases. By anticipating when verify operations are most beneficial and scheduling them in advance at optimal intervals, the patent maintains control precision while avoiding unnecessary verify operations that would waste time.
3Productivity
If all three programmed states are programmed simultaneously using full-sequence method, then programming speed is improved, but verify operation complexity increases
Solution Approach 1:
The patent segments the verify operations by target state, implementing different verify operation counts for different states (S0, S1, S2, S3). By dividing the verify operations into state-specific groups with different complexities, the patent manages the overall verify operation complexity while maintaining high programming speed through simultaneous programming of all states.
Solution Approach 2:
The patent applies different verify operation strategies to different states based on their specific requirements. Higher states (S2, S3) receive fewer verify operations while lower states (S0, S1) receive more verify operations. This local differentiation optimizes the overall system by applying appropriate verify complexity only where needed, enabling fast simultaneous programming while managing complexity.
Data Source
AI summary
Programming speed for multi-level non-volatile storage elements is increased by reducing the number of verify operations. In one approach, verify operations are initially performed for the highest state less frequently than for other, lower states based on a recognition that a wider threshold voltage distribution for the highest state can be tolerated. After a number of additional programming pulses are applied, the frequency with which the verify operations are performed for the highest state increases. For example, for a four-level device in which state C is the highest state, C-state verify operations can be started when a first B-state element has been programmed and an additional number of program pulses have been applied. The C-state verify operations can be performed after every other program pulse until a certain number of C-state elements have been fully programmed, after which the C-state verify operations can be performed after every program pulse.