Stress-Based Imminent Read Failure Detection in NVM Arrays

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Solution Overview

Problem

Current error correcting code (ECC) technologies in non-volatile memory (NVM) systems cannot accurately predict imminent read failures, particularly in safety-critical applications like automotive systems, where uncorrectable read failures could lead to accidents, and existing methods for detecting such failures are inadequate.

Innovation Solution

The implementation of a stress-based technique that applies a bulk high voltage read stress to the NVM array, followed by an array integrity check at a normal and then a margin read verify voltage level, using a combination of ECC and margin read circuits to identify imminent read failures by determining if errors are correctable at the margin read level.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If traditional ECC methods are used to detect read failures, then the system maintains simplicity and low cost, but the ability to predict imminent read failures is insufficient

Engineering Contradiction:
Improveprediction of imminent read failureVSAvoiddetection method complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent applies preliminary action by performing stress testing and margin reads before actual read failures occur. The method detects voltage threshold drift early by comparing read outcomes at normal versus margin voltages, enabling prediction of imminent failures before they affect normal operation.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent utilizes parameter changes by varying the read voltage from normal levels to margin levels. This parameter variation reveals threshold drift in memory cells that indicates impending failure, allowing detection without permanently altering the memory state or requiring additional hardware.

Inventive Principle:
Principle #35Parameter changes

2Productivity

If stress-based detection methods are implemented, then the detection speed and accuracy of imminent failures improve, but the complexity of the detection system increases

Engineering Contradiction:
Improvedetection speedVSAvoiddetection circuit complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent applies universality by using the existing ECC circuitry and memory array for dual purposes: normal operation and failure prediction. The margin read function leverages existing memory cells and control logic, avoiding the need for separate dedicated testing hardware while accelerating detection capability.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The memory array performs self-diagnosis by comparing its own read responses at different voltage levels. The ECC circuitry automatically detects and flags threshold drift conditions without requiring external testing equipment, enabling the system to self-monitor its health status efficiently.

Inventive Principle:
Principle #25Self-service

3Measurement precision

If margin reads are performed to detect threshold drift, then the precision of failure prediction improves, but the additional read operations increase time consumption

Engineering Contradiction:
Improvethreshold drift detection precisionVSAvoiddetection time
Core Design Contradiction:
Measurement precisionVSLoss of time

Solution Approach 1:

The patent implements periodic action by performing margin reads at scheduled intervals rather than continuously. This periodic monitoring at defined checkpoints balances the need for accurate threshold drift detection with acceptable time consumption, providing timely failure prediction without constant overhead.

Inventive Principle:
Principle #19Periodic action

Data Source

PatentEP2669895B1Stress-based techniques for detecting an imminent readfailure in a non-volatile memory array
Publication Date: 2019.01.23 NXP USA INC
  • EP2669895B1 patent drawingFigure 1
  • EP2669895B1 patent drawingFigure 2
  • EP2669895B1 patent drawingFigure 3

AI summary

A technique (700) for detecting an imminent read failure in a non-volatile memory array includes applying a bulk read stress to a plurality of cells of the non-volatile memory array (705) and determining whether the plurality of cells exhibit an uncorrectable error correcting code (ECC) read during an array integrity check at a margin read verify voltage level subsequent to the bulk read stress (718). The technique also includes providing an indication of an imminent read failure for the plurality of cells when the plurality of cells exhibit the uncorrectable ECC read during the array integrity check (720). In this case, the margin read verify voltage level is different from a normal read verify voltage level.