Non-volatile Memory Read Sequence Power Optimization

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Solution Overview

Problem

Current non-volatile memory devices face challenges in reducing power consumption during sensing operations due to the need for multiple passes to resolve memory states, leading to increased power consumption as more memory cells conduct current.

Innovation Solution

A memory apparatus and method that identifies memory cells with threshold voltages below specific demarcation threshold voltages and applies near zero voltage to inhibit conduction currents, reducing power consumption by locking out irrelevant cells during read operations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If massively parallel sensing is performed to improve read performance, then read speed is improved, but power consumption increases due to compounded conduction current flow

Engineering Contradiction:
Improveread speedVSAvoidpower consumption
Core Design Contradiction:
SpeedVSUse of energy by moving object

Solution Approach 1:

The read operation is segmented into multiple passes, each targeting specific memory states. In each pass, only a subset of memory cells is actively sensed while others are locked out, dividing the massively parallel operation into smaller, power-efficient groups.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Memory cells are pre-identified and locked out based on their threshold voltage characteristics before the actual sensing operation. This preliminary action prevents unnecessary current flow in cells that will not contribute to the current read pass, reducing power consumption before reading begins.

Inventive Principle:
Principle #10Preliminary action

2Measurement precision

If multiple sensing passes are executed to resolve all memory states, then measurement precision is improved, but power consumption increases due to repeated conduction current flow

Engineering Contradiction:
Improvememory state resolutionVSAvoidpower consumption
Core Design Contradiction:
Measurement precisionVSUse of energy by moving object

Solution Approach 1:

Different voltage levels and sensing conditions are applied to different subsets of memory cells based on their specific threshold voltage ranges. Each pass is optimized for detecting specific memory states, allowing precise differentiation of all states while minimizing power consumption in each individual pass.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The sensing operation is performed periodically in discrete passes with alternating active and locked-out cell groups. Each pass targets specific memory states with appropriate demarcation voltages, and the periodic locking out of cells reduces cumulative power consumption across multiple passes.

Inventive Principle:
Principle #19Periodic action

3Productivity

If all memory cells are actively sensed in parallel, then productivity is improved, but power consumption increases due to compounded conduction currents

Engineering Contradiction:
Improveread throughputVSAvoidpower consumption
Core Design Contradiction:
ProductivityVSUse of energy by moving object

Solution Approach 1:

The parallel sensing operation is segmented into multiple groups of memory cells, with each group processed in a dedicated pass. This segmentation maintains high productivity within each pass while reducing the number of simultaneously active cells, thereby lowering power consumption.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Memory cells are pre-categorized and locked out based on their threshold voltage characteristics before each pass. This preliminary classification ensures that only the necessary subset of cells is actively sensed in parallel, maintaining productivity while reducing power consumption by excluding irrelevant cells from current flow.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS11721397B2Power saving and fast read sequence for non-volatile memory
Publication Date: 2023.08.08 SANDISK TECHNOLOGIES LLC
  • US11721397B2 patent drawing
  • US11721397B2 patent drawing
  • US11721397B2 patent drawing

AI summary

A memory apparatus and method of operation are provided. The apparatus includes a page of memory cells connected to a plurality of word lines and arranged in strings and configured to retain a threshold voltage. A control circuit couples to the word lines and strings and identifies the memory cells having the threshold voltage less than a primary demarcation threshold voltage of a series for demarcating between memory states in a page read. The control circuit also identifies the memory cells having the threshold voltage less than a secondary demarcation threshold voltage of the series. The control circuit supplies a near zero voltage to the strings of the memory cells identified as having the threshold voltages less than at least one of the primary and secondary demarcation threshold voltages to inhibit conduction currents while identifying the memory cells having the threshold voltage less than a tertiary demarcation threshold voltage.