Non-Volatile Memory Read Reference Retention
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional read reference adjustment techniques for non-volatile memory (NVM) devices are inadequate due to the 'trap-up' characteristic of insulating elements, leading to erroneous reads and increased power consumption, and require recalibration at startup or reset, causing delayed initialization.
Innovation Solution
A method and device that determine and store a read reference level for each sector of a non-volatile memory array, allowing for adjustable read references to be retained in non-volatile storage, enabling accurate sensing of bit values even after power-down or reset, by using a reference configuration module and adjustable read reference generator.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a fixed read reference is used, then the device complexity is reduced, but the reliability deteriorates due to trap-up characteristics causing erroneous reads
Solution Approach 1:
The patent implements a dynamic read reference adjustment mechanism that automatically adapts the read reference level based on the trap-up characteristics of bit cells during program/erase cycles. The reference level is adjusted upward as trap-up increases, allowing the sense amplifier to maintain accurate comparisons despite changing transistor characteristics. This dynamic adaptation resolves the contradiction by sacrificing some complexity to achieve high reliability.
Solution Approach 2:
The patent employs a feedback mechanism where the sense amplifier monitors the drain current of bit cells and adjusts the read reference level accordingly. As trap-up causes the drain current to decrease, the feedback system detects this change and raises the read reference level to compensate, ensuring continued accurate reading. This feedback loop maintains reliability while managing the complexity through automated adjustment.
2Reliability
If conventional read reference adjustment techniques are used, then the reliability improves, but the loss of time increases due to recalibration at startup or reset
Solution Approach 1:
The patent performs preliminary action by automatically determining and storing the optimal read reference level during normal operation, before any reset or power-down occurs. The reference level is captured in non-volatile storage during the bit cell's operational state, so when power is restored or after reset, the stored reference is immediately reused without requiring time-consuming recalibration. This eliminates the time loss while maintaining reliability.
Solution Approach 2:
The system performs self-service by automatically managing its own reference level adjustment without external intervention. The sense amplifier continuously monitors bit cell characteristics and self-adjusts the read reference, storing the optimized level in non-volatile memory. This self-service capability ensures that after reset, the system can immediately resume operation with the stored reference, avoiding time loss while maintaining accuracy.
3Reliability
If the read reference is adjusted to account for trap-up, then the reliability improves, but the use of energy increases due to increased power consumption
Solution Approach 1:
The patent applies parameter changes by dynamically adjusting the read reference level parameter in response to trap-up characteristics. As the transistor threshold voltage increases due to trap-up, the read reference is raised to maintain the comparison accuracy. This parameter adaptation allows the system to maintain reliability without requiring excessive power, as the adjustment is made only when necessary based on operational conditions.
Data Source
AI summary
A read reference level of a plurality of read reference is determined for a set of bit cells of a non-volatile memory array. An indicator of the read reference level is stored in a non-volatile storage location associated with the set of bit cells. The indicator of the read reference level is accessed in response to a read access operation to the set of bit cells and a value stored at a memory location of the set of bit cells is sensed based on the indicator of the read reference level, whereby the memory location of the set of bit cells is associated with the read access operation.