Single-Ended NVM Read Scheme Using Distributed Common Mode Feedback
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Single-ended read systems for non-volatile memory (NVM) are less accurate and have a limited range of operation compared to differential systems, necessitating an improved read operation for efficient data retrieval.
Innovation Solution
A non-volatile memory system that employs a bit line controller with sense amps connected to bit cells, determining data content based on the time required for a current to raise a voltage, using a reference bit cell for feedback to adjust the read operation, effectively creating a pseudo-differential system with improved accuracy and range.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a single-ended read system is used, then area, power consumption and speed are improved, but measurement precision and reliability deteriorate
Solution Approach 1:
The patent implements a feedback mechanism where the sense amp output is fed back to adjust the common mode voltage level. This feedback loop allows the system to compensate for process variations and improve read accuracy without requiring a fully differential architecture. The feedback signal modifies the common mode level dynamically based on the sensed data, resolving the contradiction between accuracy and complexity.
Solution Approach 2:
The patent introduces a common mode feedback circuit as an intermediary element that mediates between the single-ended sense amp output and the reference bit cell. This intermediary circuit adjusts the common mode voltage to optimize the read operation, enabling improved precision while maintaining the simplicity of single-ended operation. The common mode feedback acts as a mediator that bridges the gap between simple single-ended design and accurate differential performance.
2Adaptability or versatility
If a single-ended read system is used, then area and power are reduced, but operational range and accuracy are limited
Solution Approach 1:
The patent employs dynamic adjustment of the common mode voltage level through feedback control. The common mode level is not fixed but dynamically adapts based on the sensed signal and reference bit cell characteristics. This dynamic behavior allows the system to maintain high accuracy across a wide range of operating conditions, resolving the contradiction between adaptability and precision.
Solution Approach 2:
The patent changes the common mode voltage parameter dynamically during the read operation. By adjusting this critical parameter based on feedback from the sense amp and reference bit cell, the system can optimize its performance across different operating ranges. This parameter change strategy enables both wide operational range and high read accuracy simultaneously.
3Reliability
If a reference bit cell is added for feedback, then read accuracy is improved, but device complexity increases
Solution Approach 1:
The patent merges the reference bit cell functionality with the sense amp circuitry in an integrated manner. Rather than adding completely separate reference and sensing circuits, the design combines them to share common resources and control logic. This merging approach improves reliability through better comparison while minimizing the increase in overall circuit complexity.
Solution Approach 2:
The reference bit cell is designed to serve multiple functions: providing a reference current for comparison, establishing a common mode voltage level, and participating in the feedback loop. This multi-functionality reduces the need for separate dedicated circuits, thereby improving data retention reliability without proportionally increasing circuit complexity.
Data Source
AI summary
A non-volatile memory system includes an array of bit cells arranged in rows and columns and configured to store bits of data, a reference bit cell, a plurality of bit lines connectable to the bit cells in the array and connecting to the reference bit cell, and a bit line controller. The bit line controller comprises a plurality of sense amps connected to the bit cells by the bit lines. The bit line controller determines the contents of the bit cells based on times tcell compared to a time tref, where tcell is the time required for a current Icell generated by one of the bit cells to raise a voltage Vsense of one of the sense amps by an amount ΔV, and tref is the time required for a current Iref generated by the reference bit cell to raise the voltage Vsense of another one of the sense amps by the same ΔV. ΔV increases monotonically as a function of Iref.