Non-Volatile Memory Read Device with Timing Control
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Solution Overview
Problem
Existing non-volatile memory reading devices face high power consumption and increased read access time due to the continuous operation of electronic components during each verification cycle, especially when the microprocessor unit operates at low frequency.
Innovation Solution
A reading device with a timing mechanism that independently manages the read duration of selected memory cells using a dummy cell and delay capacitor, allowing for the precise control of sense amplifier activation and deactivation, thereby reducing power consumption and optimizing read time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If the reference current is reduced to lower power consumption, then electrical consumption is reduced, but read access time is increased
Solution Approach 1:
The sense amplifiers are activated periodically in bursts corresponding to actual read operations rather than continuously. The timing means generates periodic activation signals that enable sense amplifiers only during read cycles, reducing overall power consumption while maintaining fast read access times when needed.
Solution Approach 2:
The system dynamically adjusts the operational state of sense amplifiers based on actual read requirements. The timing means controls the activation and deactivation of sense amplifiers in real-time, allowing the system to transition between low-power standby and high-speed read modes as needed.
2Ease of operation
If sense amplifiers remain in operation during each verification cycle, then reading can be performed, but electrical consumption remains high especially at low microprocessor frequencies
Solution Approach 1:
The timing means generates periodic activation signals that enable sense amplifiers only during actual read cycles. This periodic activation ensures reading capability is available when needed while minimizing electrical consumption during idle periods, especially important when microprocessor frequency is low.
Solution Approach 2:
The timing means receives feedback from the microprocessor unit about read requirements and accordingly controls the activation of sense amplifiers. This feedback mechanism ensures sense amplifiers are active only when reading is actually required, optimizing the balance between operational capability and power consumption.
3Adaptability or versatility
If reading time is not precisely determined, then flexibility is maintained, but electrical consumption cannot be optimized
Solution Approach 1:
The timing means dynamically determines the precise reading duration based on the specific read operation requirements. This dynamic timing allows the system to optimize electrical consumption by activating sense amplifiers only for the exact duration needed, while maintaining flexibility to handle different reading scenarios.
Solution Approach 2:
The system changes the time parameter of sense amplifier operation based on actual read requirements. The timing means adjusts the activation duration of sense amplifiers to match the precise reading time needed, optimizing power consumption while maintaining adaptability to different memory read scenarios.
Data Source
Figure 1
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Figure 3a~3b
AI summary
The device has a temporization unit activated at start of each reading cycle, to provide a reference signal controlling reading duration of selected cell independent of a microprocessor unit, where the reading duration is determined for reading all valid data of the memory cell selected in each reading cycle. The temporization unit has a reference dummy cell (TF) connected to a reference detection amplifier (3), which provides a reference signal (rdmon), and a temporization capacitor (Cgap) is connected to the dummy cell. An independent claim is also included for a method for actuating a reading device of a non-volatile memory.