NVM Read Voltage Calibration for Cross-Temperature Error Control

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Solution Overview

Problem

Current non-volatile memory (NVM) devices, such as 3D NAND flash memory, experience significant reliability and data transfer performance degradation due to cross-temperature effects, which arise from differences between programming and reading temperatures, leading to increased bit error rates.

Innovation Solution

A method and apparatus that selects a master set of read voltages providing the lowest acceptable error rate performance over a range of cross-temperature differential values, which is then used irrespective of the NVM temperature, and can be adjusted based on factors like program/erase counts, data aging, and word line addresses.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If temperature-specific read voltage sets are used to optimize read performance at specific temperatures, then read performance at those temperatures is improved, but device complexity increases due to the need to store and select multiple voltage sets

Engineering Contradiction:
Improveread performanceVSAvoidvoltage set management
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent applies universality by developing a single master set of read voltages that functions across all temperature ranges. Instead of creating separate voltage sets for different temperature conditions, the invention makes one voltage set universally applicable, thereby improving read performance across the full temperature range while eliminating the complexity of storing and managing multiple temperature-specific voltage sets.

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Device complexity

If a single master set of read voltages is used across all temperature ranges, then device complexity is reduced, but read performance degrades at temperatures far from the calibration temperature

Engineering Contradiction:
Improvevoltage set managementVSAvoidread performance
Core Design Contradiction:
Device complexityVSReliability

Solution Approach 1:

The patent applies local quality by creating customized adjustments to the master voltage set based on specific operating conditions such as program/erase count, data aging, and temperature range. Rather than using a completely universal voltage set, the invention allows local optimization by applying condition-specific adjustments to the base master set, thereby maintaining simplicity while recovering performance at extreme temperatures.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent applies preliminary action by pre-calculating and storing adjustment values for the master voltage set that account for various operating conditions including different program/erase counts, data aging effects, and temperature ranges. These adjustments are prepared in advance and applied during operation, eliminating the need for real-time complex calculations while maintaining optimal read performance across varying conditions.

Inventive Principle:
Principle #10Preliminary action

3Reliability

If read voltages are optimized for narrow temperature ranges, then read performance within that range is improved, but adaptability to wide temperature variations deteriorates

Engineering Contradiction:
Improveread performanceVSAvoidtemperature range coverage
Core Design Contradiction:
ReliabilityVSAdaptability or versatility

Solution Approach 1:

The patent applies universality by constructing a master voltage set designed to function across the entire operating temperature range rather than being optimized for narrow ranges. This universal approach ensures adaptability to wide temperature variations while maintaining acceptable read performance across all conditions, resolving the contradiction between narrow-range optimization and broad-range adaptability.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS11017850B2Master set of read voltages for a non-volatile memory (NVM) to mitigate cross-temperature effects
Publication Date: 2021.05.25 SEAGATE TECH LLC
  • US11017850B2 patent drawing
  • US11017850B2 patent drawing
  • US11017850B2 patent drawing

AI summary

Method and apparatus for managing data in a non-volatile memory (NVM) of a storage device, such as a solid-state drive (SSD). In some embodiments, first data are read from the NVM using an initial set of read voltages over a selected range of cross-temperature differential (CTD) values comprising a difference between a programming temperature at which the first data are programmed to the NVM cells and a reading temperature at which the first data are subsequently read from the NVM cells. A master set of read voltages is thereafter selected that provides a lowest acceptable error rate performance level over the entirety of the CTD range, and the master set of read voltages is thereafter used irrespective of NVM temperature. In some cases, the master set of read voltages may be further adjusted for different word line addresses, program/erase counts, read counts, data aging, etc.