Non-Volatile Memory Recovery via Moving Read Reference
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Solution Overview
Problem
Non-volatile memory (NVM) arrays face challenges in accurately reading data due to threshold voltage drift, leading to data corruption and loss, especially in multi-level cell (MLC) systems where voltage ranges for different states are smaller, causing false reads and requiring efficient methods to compensate for variations.
Innovation Solution
The use of error detection (ED) bits and a 'moving read reference' technique, where read reference voltages are adjusted based on the number of cells found in each program state compared to expected values, allowing for accurate data recovery by shifting the read reference and re-reading data until alignment with ED bits is achieved.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If read reference voltages are fixed for MLC states, then device complexity is reduced, but measurement precision deteriorates due to threshold voltage drift causing false reads
Solution Approach 1:
The patent implements dynamic read reference voltage adjustment by introducing a reference voltage generator that modifies read reference voltages based on detected threshold voltage drift. The system dynamically adapts read reference voltages for different program states rather than using fixed references, allowing accurate data reading despite Vt drift in MLC cells.
Solution Approach 2:
The patent employs feedback mechanisms where read reference voltages are adjusted based on feedback from threshold voltage measurements. The system detects actual Vt values of programmed cells and uses this information to adjust read reference voltages accordingly, creating a closed-loop system that compensates for Vt drift and ensures accurate data retrieval.
2Productivity
If programming pulses are applied continuously, then programming speed is improved, but reliability deteriorates due to inability to detect and correct programming failures
Solution Approach 1:
The patent implements periodic verification during the programming process by applying programming pulses in sequences separated by verify operations. The system programs a portion of cells, verifies their state, and based on verification results, decides whether to continue programming or switch to recovery mode, creating a periodic check-in mechanism that balances speed and reliability.
Solution Approach 2:
The patent performs preliminary verification after programming pulses are applied to detect programming failures before they propagate. By verifying cell states immediately after programming attempts and detecting failures early, the system can switch to recovery procedures while maintaining overall programming efficiency and preventing complete data loss.
3Ease of operation
If SRAM bits are flipped continuously during programming, then data tracking is improved, but loss of information worsens when programming fails and original user data is lost
Solution Approach 1:
The patent introduces ED bits as intermediary elements that store expected data states separately from the SRAM buffer. These ED bits serve as a reference to verify whether programming succeeded or failed, allowing the system to recover original user data by comparing against ED bits when programming failures are detected, thus preventing information loss.
Solution Approach 2:
The patent implements a recovery mechanism that discards potentially corrupted data from the SRAM buffer when programming failures are detected and recovers original user data by comparing against ED bits. The system can identify which bits were successfully programmed versus which failed, discarding only the failed portions and recovering the original data for re-programming.
Data Source
AI summary
Disclosed are methods and circuits for performing recovery associated with programming of non-volatile memory (NVM) array cells. According to embodiments, there are provided methods and circuits for programming NVM cells, including: (1) erasing NVM array cells; (2) loading an SRAM with user data; (3) if programming is successful, then flipping bits in the SRAM; and (4) if programming is not successful, reading data back from the array to the SRAM.