NVM Redundancy via Cell Inversion for Yield
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Solution Overview
Problem
Existing redundancy schemes for non-volatile memories require significant additional logic, increasing chip area and logic overhead, which is not optimal for maximizing manufacturing yield and minimizing logic overhead.
Innovation Solution
A redundancy scheme that utilizes defective cells in non-volatile memories to store data by setting leaky cells to a permanent logic state and using inversion status cells to determine whether to invert or maintain the logic states of program data, thereby reclaiming defective cells and reducing the need for additional logic.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If existing redundancy schemes are used to handle defective cells, then manufacturing yield is improved, but chip area and logic overhead increase significantly
Solution Approach 1:
The patent recovers defective cells by setting them to a permanent logic state (e.g., logic 0 for leaky cells) and uses inversion status cells to manage the inversion of stored data. This allows defective cells to be reused rather than discarded, improving manufacturing yield without requiring additional spare cells that would increase chip area.
Solution Approach 2:
The patent uses inversion status cells to control whether data is stored or inverted in defective cells. By inverting the logic state of data stored in conjunction with defective cells, the system can accommodate the permanent logic state of defective cells while maintaining correct data representation, thereby avoiding the need for additional logic circuitry.
2Reliability
If existing redundancy schemes are used to handle defective cells, then manufacturing yield is improved, but logic overhead increases
Solution Approach 1:
The patent recovers defective cells by setting them to a permanent logic state and uses inversion status cells to manage data inversion. This approach reuses existing cells rather than adding redundant logic circuits, thereby improving manufacturing yield while minimizing logic overhead.
Solution Approach 2:
The inversion status cells serve multiple functions: they control data inversion for defective cells, indicate the inversion state during read operations, and enable the memory system to handle defective cells without additional dedicated redundancy logic. This multi-functionality reduces overall logic overhead while maintaining manufacturing yield.
3Area of stationary object
If defective cells are reclaimed and reused, then chip area is reduced, but additional logic is required to manage inversion status
Solution Approach 1:
The inversion status cells perform multiple functions: controlling data inversion for defective cells, indicating inversion state during reads, and enabling defective cell management without dedicated redundancy logic. This multi-functionality justifies the minimal additional logic while achieving significant chip area reduction through defective cell reuse.
Solution Approach 2:
The patent changes the logic state parameter of defective cells to a permanent state (e.g., logic 0) and uses inversion status cells to manage the inversion of data. This parameter change allows defective cells to be reused without requiring complex additional logic, as the inversion mechanism is integrated into the existing memory structure.
Data Source
AI summary
A redundancy scheme for Non-Volatile Memories (NVM) is described. This redundancy scheme provides means for using defective cells in non-volatile memories to increase yield. The algorithm is based on inverting the program data for data being programmed to a cell grouping when a defective cell is detected in the cell grouping. Defective cells are biased to either “1” or “0” logic states, which are effectively preset to store its biased logic state. A data bit to be stored in a defective cell having a logic state that is complementary to the biased logic state of the cell results in the program data being inverted and programmed. An inversion status bit is programmed to indicate the inverted status of the programmed data. During read out, the inversion status bit causes the stored data to be re-inverted into its original program data states.