Non-Volatile Memory Redundancy via Physical Plane Separation
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Solution Overview
Problem
Non-volatile memory devices, such as Flash memory, are susceptible to defects that can result in data loss due to semiconductor crystal defects and other defect mechanisms, with existing redundancy schemes being inadequate in preventing data corruption across multiple memory planes.
Innovation Solution
A redundancy mapping is defined between physical memory blocks in two planes of a memory die, ensuring a predefined physical separation between corresponding blocks to store data in one plane and redundancy information in another, derived from the die's layout to maximize separation and reduce the likelihood of defects affecting both.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If redundancy information is stored in adjacent memory blocks across multiple planes, then data protection against single-block failures is improved, but the risk of data loss increases when semiconductor defects affect multiple adjacent blocks
Solution Approach 1:
The patent segments the memory die into multiple independent planes, each with its own separate memory blocks. Redundancy information is stored in blocks belonging to different planes rather than adjacent blocks within the same plane. This segmentation isolates defects to specific planes, preventing them from affecting both data and redundancy information simultaneously.
Solution Approach 2:
The patent introduces a new dimension of physical separation by utilizing the plane dimension in the memory hierarchy. Instead of merely separating redundancy information in the block dimension (adjacent blocks), it separates them across the plane dimension (different planes), creating multi-dimensional spatial distribution that reduces defect correlation.
2Reliability
If physical separation between data blocks and redundancy blocks is increased across memory planes, then the likelihood of defects affecting both is reduced, but memory address mapping complexity increases
Solution Approach 1:
The patent pre-establishes a mapping relationship between data blocks and redundancy blocks across different planes before actual data storage operations. This mapping table is prepared in advance, allowing the memory controller to quickly translate logical addresses to physical addresses without real-time computation, thus reducing mapping complexity while maintaining physical separation.
Solution Approach 2:
The patent introduces a mapping table as an intermediary layer between the logical address space and physical memory blocks. This mapping table abstracts the complex physical separation requirements, allowing simple logical addresses to map to physically separated blocks across different planes without exposing the complexity to users or higher-level systems.
3Reliability
If redundancy mapping is based on physical die layout with predefined separation criteria, then defect resistance is improved, but manufacturing flexibility is reduced
Solution Approach 1:
The patent defines specific parameter criteria for physical separation, such as minimum plane separation distances and specific plane pair combinations. These parameter specifications allow manufacturers to control defect resistance through standardized design rules while maintaining flexibility in actual manufacturing processes, as the criteria can be adjusted based on process capabilities and defect profiles.
Data Source
AI summary
A method includes, for a memory die including at least first and second memory planes, each including multiple physical memory blocks, holding a definition of a redundancy mapping between first memory blocks in the first memory plane and respective second memory blocks in the second memory plane, such that a physical separation on the die between each first physical memory block and a corresponding second physical memory block meets a predefined criterion. Data is stored in one or more first physical memory blocks in the first memory plane. Redundancy information is stored relating to the data in one or more second physical memory blocks in the second memory plane that are mapped by the redundancy mapping to the one or more first physical memory blocks.