Dynamic Reference Current Adjustment for NVM Cell Lifetime

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Solution Overview

Problem

Non-volatile memory (NVM) cells experience detrimental effects on their lifetime due to excessive programming and erase cycles, which alter their electrical operating characteristics, making it difficult to achieve programmed and erased states effectively.

Innovation Solution

The solution involves adjusting the reference current for each NVM block based on its cycling performance and data retention requirements, taking into account temperature variations, to reduce the number of program/erase pulses, thereby extending the lifetime of NVM cells. This is achieved by using a sense amplifier with a variable reference current source that adjusts the erase and program verify reference currents when the number of pulses exceeds a predetermined threshold.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If the number of program/erase cycles is increased to improve data storage capacity utilization, then the productivity is improved, but the lifetime of NVM cells deteriorates due to altered electrical operating characteristics

Engineering Contradiction:
Improvedata storage capacity utilizationVSAvoidlifetime of NVM cells
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The reference current is made dynamically adjustable based on the cycling history of each NVM block. The system transitions from a static reference current to a dynamic one that adapts to the block's wear level, allowing the memory system to maintain reliable operation even after excessive programming and erase cycles have altered the electrical characteristics of the cells

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The system changes the reference current parameter in response to detected degradation in NVM block performance. By monitoring the number of program/erase cycles and adjusting the reference current accordingly, the system compensates for altered electrical operating characteristics and maintains accurate state verification throughout the NVM's operational lifetime

Inventive Principle:
Principle #35Parameter changes

2Device complexity

If a fixed reference current is used for all NVM blocks, then the device complexity is reduced, but the measurement precision deteriorates when NVM blocks have different cycling performance

Engineering Contradiction:
Improvereference current managementVSAvoidstate verification accuracy
Core Design Contradiction:
Device complexityVSMeasurement precision

Solution Approach 1:

Each NVM block is assigned its own adjusted reference current based on its specific cycling history and wear level. This local customization of the reference current parameter allows each block to be verified with the precision it requires, rather than using a one-size-fits-all approach that would be inaccurate for blocks with different cycling performance

Inventive Principle:
Principle #3Local quality

3Manufacturing precision

If the number of program/erase pulses is increased to ensure complete programming and erasing, then the manufacturing precision is improved, but the duration of action increases which reduces productivity

Engineering Contradiction:
Improveprogram/erase completion accuracyVSAvoidprogram/erase operation time
Core Design Contradiction:
Manufacturing precisionVSDuration of action of moving object

Solution Approach 1:

The system uses feedback from verifying the programmed and erased states to determine when the program/erase operations are complete. By using an adjusted reference current that accounts for cell degradation, the verification process becomes more accurate, allowing the system to reliably detect completion with fewer pulses and reduce the overall operation time

Inventive Principle:
Principle #23Feedback

Data Source

PatentUS8995200B1Non-volatile memory (NVM) with dynamically adjusted reference current
Publication Date: 2015.03.31 NXP USA INC
  • US8995200B1 patent drawing
  • US8995200B1 patent drawing
  • US8995200B1 patent drawing

AI summary

A sense amplifier is configured to sense a current from a selected bit cell of a non-volatile memory array and compare the sensed current to a reference current to determine a logic state stored in the bit cell. A controller is configured to perform a program/erase operation on at least a portion of the memory array to change a logic state of at least one bit cell of the portion of the memory array; determine a number of program/erase pulses applied to the at least one bit cell during the program/erase operation to achieve the change in logic state; and when the number of program/erase pulses exceeds a pulse count threshold, adjust the reference current of the sense amplifier for a subsequent program/erase operation.