Non-Volatile Memory Refresh Management During Power-Down

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Solution Overview

Problem

Existing memory sub-systems face challenges in efficiently managing background media scans for non-volatile memory devices, leading to potential data loss and increased read trigger rates due to power-down operations interrupting refresh operations.

Innovation Solution

The system delays the power-down operation of the memory sub-system until refresh data from qualifying blocks is completely written back to new memory blocks, ensuring data integrity and reducing read trigger rates by maintaining continuous refresh operations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Use of energy by moving object

If power-down operations are performed frequently to save energy, then energy consumption is reduced, but data loss occurs and read trigger rates increase

Engineering Contradiction:
Improveenergy consumptionVSAvoiddata integrity
Core Design Contradiction:
Use of energy by moving objectVSReliability

Solution Approach 1:

The system performs preliminary actions by detecting power-down events and identifying qualifying memory blocks before the power-down occurs. It proactively initiates refresh operations for these blocks, ensuring data is rewritten to new blocks before power is lost, thus preventing data loss while allowing frequent power-down cycles

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The system introduces an intermediary mechanism - a queue data structure - that mediates between the power-down operation and the refresh operation. The queue stores identifiers of blocks needing refresh, allowing the system to manage and coordinate these operations efficiently without direct interference between power management and data integrity mechanisms

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If background media scans are performed continuously to maintain data integrity, then data retention is improved, but system latency increases

Engineering Contradiction:
Improvedata retentionVSAvoidsystem latency
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

Instead of continuous scanning, the system implements periodic background media scans that target only qualifying blocks identified through power-down events. This periodic approach maintains data retention by refreshing blocks when needed while minimizing unnecessary scans, thereby reducing system latency

Inventive Principle:
Principle #19Periodic action

Solution Approach 2:

The system applies local quality by differentiating between qualifying blocks (those affected by power-downs) and non-qualifying blocks. Refresh operations are selectively applied only to qualifying blocks rather than uniformly to all blocks, optimizing resource usage and reducing overall system latency while maintaining data integrity where it matters most

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS20250181247A1Efficiency-improved background media scan management of non-volatile memory devices
Publication Date: 2025.06.05 MICRON TECHNOLOGY INC
  • US20250181247A1 patent drawing
  • US20250181247A1 patent drawing
  • US20250181247A1 patent drawing

AI summary

A system includes an integrated circuit (IC) memory device with memory cells. A volatile memory device includes a queue to store indicators for one or more blocks of the memory cells that are to be refreshed. A processing device is operatively coupled to the IC memory device and the volatile memory device. The processing device detects initiation of a power-down operation of the system. In response to detecting the initiation of the power-down operation, the processing devices detects one or more indicators remain in the queue corresponding to the one or more blocks and sends a signal to a host system coupled to the processing device. The signal indicates to the host system to wait to complete the power-down operation until writing refresh data, from the one or more blocks, to one or more erased blocks of the IC memory device is complete.