Non-Volatile Memory Array Segment Reference Voltage Adaptation
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Solution Overview
Problem
Non-volatile memory (NVM) cells exhibit varying native threshold voltage distributions across different segments of an array, leading to potential errors in logical state interpretation due to insufficient margins between reference levels, especially under temperature and voltage changes.
Innovation Solution
A system and method that determine the lowest reference voltage level for each array segment, storing it in a reference voltage table, which can indicate either an absolute voltage or an offset from a global reference, allowing for segment-specific verification of logical states in NVM cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single global reference voltage level is used for the entire NVM array, then device complexity is reduced, but measurement precision deteriorates due to insufficient margins between reference levels across segments with different native threshold voltage distributions
Solution Approach 1:
The NVM array is divided into multiple segments, each with its own locally optimized reference voltage level. This segmentation allows each segment to have a reference voltage tailored to its specific native threshold voltage distribution, improving measurement precision without requiring a completely complex global system. The patent implements this by creating segment-specific reference voltages that are compared against cell currents in respective segments.
Solution Approach 2:
Each segment of the NVM array is provided with a reference voltage level that is locally optimized for that segment's characteristics. The reference voltage for each segment is set based on the highest native threshold voltage within that segment, ensuring adequate margins for accurate logical state verification in local conditions rather than using a one-size-fits-all global reference.
2Reliability
If the lowest reference voltage is set slightly higher than the highest native threshold voltage of the array, then reliability is improved for cells in high-threshold segments, but cycle margin deteriorates for cells in low-threshold segments
Solution Approach 1:
The array is segmented so that each segment has its own reference voltage level optimized for that segment's native threshold voltage distribution. This prevents the need to set a single global reference voltage that would compromise margins in any particular segment, as each segment operates with a reference appropriate to its characteristics.
Solution Approach 2:
Each segment receives a reference voltage level that is locally adapted to its specific native threshold voltage characteristics. The reference voltage for each segment is determined by the highest native threshold voltage within that segment, ensuring that each segment maintains adequate cycle margins and reliability for its local conditions.
3Measurement precision
If segment-specific reference voltage levels are determined and stored in a reference voltage table, then measurement precision is improved for logical state verification, but device complexity increases
Solution Approach 1:
The reference voltage levels for each segment are determined in advance during manufacturing and stored in a reference voltage table. This preliminary action allows the system to quickly retrieve and use pre-calculated segment-specific reference voltages during operation, improving measurement precision without adding significant operational complexity. The table stores the highest native threshold voltage for each segment, which is used to set the appropriate reference level.
Data Source
AI summary
As part of the present invention, a memory cell may be operated using reference cells having a threshold offset circuit. According to some embodiments of the present invention, a threshold offset value may be determined for a memory cell to be operated based on a location (e.g. memory segment within a memory array) of the memory cell. An input offset circuit of a global reference cell may be adjusted by the threshold offset value for the memory cell; and the memory cell may be operated (e.g. read, written or erased) using the global reference cell whose input offset circuit has been adjusted by the threshold offset value. According to some embodiments of the present invention global reference cells may consist of multiple sets of reference cells, wherein, according to some aspects, each set of the multiple sets of reference cells may be used for operating a different memory array segment. According to other aspects, each set of the multiple sets of reference cells may be used for operating a different state of memory array cells.