Non-Volatile Memory Select Gate Spacer Design
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Solution Overview
Problem
NAND-type array flash memory structures often experience short circuits at the contact window and select gate, leading to reduced product yield due to insufficient isolation and process inaccuracies during fabrication.
Innovation Solution
The non-volatile memory structure incorporates select gate structures with tapered corners and spacers on the sidewalls, along with a method that includes forming dielectric and conductive layers sequentially, using silicon oxide and doped poly-silicon materials, to create a design that prevents short circuits by increasing the distance between the select gate and contact window, and employs spacers as a self-aligned etching mask for improved process tolerance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional flash memory structures are used with standard contact window formation, then manufacturing process is simple, but short circuits occur between contact window and select gate leading to reduced yield
Solution Approach 1:
The select gate structure is segmented into multiple components including a select gate electrode, cap layer, and spacer. The contact window formation is segmented into multiple steps with different etching processes. This segmentation allows for better control of each component's dimensions and positioning, preventing short circuits while maintaining manufacturing feasibility.
Solution Approach 2:
Spacers are formed on the sidewalls of the select gate structure before contact window formation. This preliminary action creates a protective barrier that prevents the contact window etch from reaching the select gate, eliminating short circuit risks. The spacers serve as pre-positioned protective elements that guide subsequent processing steps.
2Area of stationary object
If contact window is formed closer to select gate to increase integration density, then area utilization improves, but short circuit risk increases
Solution Approach 1:
A spacer structure serves as an intermediary element between the select gate and the contact window. This spacer acts as a mediating barrier that physically separates the two components, preventing direct contact and potential short circuits. The spacer allows the contact window to be positioned closer to the select gate for better area utilization while maintaining reliable electrical isolation.
Solution Approach 2:
The solution moves the isolation mechanism from the planar dimension to the vertical dimension by forming spacers on the sidewalls of the select gate structure. This vertical barrier provides effective separation without consuming additional horizontal space, allowing high area utilization while preventing short circuits through three-dimensional structural design.
3Ease of manufacture
If standard etching process is used for contact window formation, then manufacturing is straightforward, but process tolerance is insufficient leading to short circuits
Solution Approach 1:
The spacer structure serves as a self-aligned etching mask that automatically defines the contact window position and dimensions. The spacer's sidewall acts as a self-generated barrier that prevents over-etching and ensures precise contact window formation without requiring additional alignment steps. This self-service mechanism inherently provides process tolerance and prevents manufacturing variations from causing short circuits.
Solution Approach 2:
The spacer structure provides a protective cushion before the contact window etch reaches the select gate. This beforehand cushioning ensures that even if etching parameters vary or alignment is slightly off, the spacer will prevent the etch from reaching the select gate, providing built-in process tolerance and protecting against manufacturing variations.
Data Source
AI summary
A substrate having a first dielectric layer, a first conductive layer and a second dielectric layer thereon is provided. A part of the second dielectric layer is removed to form a first opening having both ends with a select gate region respectively. The select gate region is constituted by a region with the second dielectric layer and a region without the second dielectric layer. A second conductive layer is formed to cover the second dielectric layer. A cap layer is formed on the second conductive layer. The cap layer, the second conductive layer, the second dielectric layer and the first conductive layer are patterned to form gate structures. The cap layer, the second conductive layer, the second dielectric layer and the first conductive layer between two adjacent select gate regions are removed to form a select gate structure. A doped region is formed in the substrate.