Non-Volatile Memory Error Detection via Selective CRC
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Solution Overview
Problem
Existing error correction techniques for non-volatile memories (NVMs) introduce significant latency and complexity, making them inefficient for high-speed operations and requiring computationally expensive training processes.
Innovation Solution
A non-volatile memory controller with a cyclic redundancy check (CRC) circuit and calibration circuit that detects errors and re-trains the NVM device by comparing generated and received CRC codes, activating re-training only when necessary to minimize latency and complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If CRC is performed on every NVM read operation, then error detection capability is improved, but memory operation speed deteriorates significantly
Solution Approach 1:
The patent applies partial action by performing CRC error detection selectively rather than on every read operation. The system monitors error rates and only activates full CRC checking when error conditions are detected, thereby maintaining error detection capability while avoiding the performance penalty of continuous CRC operations.
Solution Approach 2:
The patent implements periodic error detection by using monitoring intervals and threshold-based triggering. Instead of continuous CRC checking, the system periodically samples error conditions and activates full error detection only when necessary, balancing reliability and speed requirements.
2Reliability
If NVM training is performed to calibrate NVM circuitry and minimize data errors, then error correction capability is improved, but computational expense and circuit complexity increase
Solution Approach 1:
The patent applies preliminary action by performing NVM training and calibration during manufacturing or initial system setup, storing the resulting calibration parameters in the NVM device. This preliminary training eliminates the need for complex real-time training circuits during operation, reducing device complexity while maintaining error correction capability.
Solution Approach 2:
The patent uses copying by storing calibration parameters and training data in the NVM device itself rather than requiring complex external training circuits. The trained parameters are copied into the NVM during manufacturing, allowing the device to self-correct errors without additional complex circuitry.
Data Source
AI summary
The present disclosure, in various embodiments, describes technologies and techniques for detecting errors in a non-volatile memory (NVM) device prior to performing re-training/recalibration. A processing device in a NVM controller detects a cyclic redundancy check (CRC) condition for detecting error in the NVM device, and a re-training condition that is based on the CRC condition. A CRC circuit generates CRC code when a CRC condition is detected, and the processing is configured to compare CRC code received from the NVM controller with the generated CRC code to detect error. A calibration circuit then re-trains the NVM device if the CRC circuit detects error and the re-training condition has been met.