Non-Volatile Memory Self-Convergence During Erase
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Solution Overview
Problem
Conventional non-volatile memory devices face inefficiencies in correcting over-erased cells due to manufacturing variances, leading to leakage currents that hinder accurate reads and require additional circuitry and time for erase cycles.
Innovation Solution
Implementing self-convergence during the erase cycle by controlling the physical aspects of dielectric layers and the gate structure, including ramping the erase voltage, to create a lateral and transient vertical field that corrects over-erased cells without additional circuitry or time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional erase methods are used on non-volatile memory cells, then erase operation is performed, but manufacturing variances cause over-erase conditions leading to leakage currents and inaccurate reads
Solution Approach 1:
The patent implements self-convergence during the erase cycle where the memory device automatically corrects over-erase conditions without external intervention. The physical aspects of the dielectric layers and gate structure enable the cells to self-regulate and converge to a positive threshold voltage, eliminating the need for additional correction circuitry or operations.
Solution Approach 2:
The patent utilizes ramping the erase voltage applied to the control gate during the erase cycle. By dynamically changing the voltage parameter rather than applying a fixed voltage, the system achieves better control over the erase process, allowing cells to converge to the desired threshold voltage distribution and preventing over-erase conditions.
2Reliability
If additional circuitry is added to correct over-erased cells, then read accuracy improves, but device complexity increases
Solution Approach 1:
The patent eliminates the need for additional correction circuitry by implementing self-convergence through the inherent physical properties of the memory cell structure. The dielectric layers and gate structure are designed to automatically correct over-erase conditions, replacing complex correction circuitry with a simplified self-regulating mechanism.
Solution Approach 2:
The patent removes the need for separate correction circuitry and operations by integrating the correction function into the normal erase cycle itself. The self-convergence mechanism is embedded in the fundamental operation of the memory cell, eliminating redundant components and simplifying the overall device architecture.
3Manufacturing precision
If additional time is allocated for erase correction, then threshold voltage distribution narrows, but erase cycle duration increases
Solution Approach 1:
The patent achieves self-convergence during the normal erase cycle without requiring additional correction time. The ramping erase voltage continuously adjusts the erase process, allowing cells to converge to the desired threshold voltage distribution as part of the standard erase operation, eliminating separate correction time.
Solution Approach 2:
By ramping the erase voltage during the erase cycle, the patent dynamically optimizes the erase process to achieve narrow threshold voltage distribution within the standard erase time. The changing voltage parameter enables continuous adjustment that prevents over-erase conditions while maintaining fast erase speeds.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach ensures all cells converge to a positive threshold voltage efficiently and quickly, achieving a narrow threshold voltage distribution without extending the erase cycle, thus addressing the inefficiencies of conventional solutions.
Implementation Method 1
controlling the physical aspects of dielectric layers and the gate structure... to create a lateral and transient vertical field that corrects over-erased cells
Implementation Method 2
ramping the erase voltage applied to the control gate during the erase cycle... ensures all cells converge to a positive threshold voltage
Data Source
AI summary
A non-volatile memory device implements self-convergence during the normal erase cycle through control of physical aspects, such as thickness, width, area, etc., of the dielectric layers in the gate structure as well as of the overall gate structure. Self-convergence can also be aided during the normal erase cycle by ramping the erase voltage applied to the control gate during the erase cycle.