Storage Architecture With NVM Sets for End-to-End Tenant Isolation
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Solution Overview
Problem
Existing multi-tenant systems struggle to provide effective performance isolation for a large number of tenants, limiting the applicability of existing solutions.
Innovation Solution
A new architecture for storage devices, such as Solid State Drives (SSDs), that implements Non-Volatile Memory (NVM) Sets and submission queues (SQs) with Quality of Service (QoS) levels to achieve end-to-end performance isolation among tenants, using a Weighted Round Robin (WRR) scheduling algorithm and QoS-based partitioning of NAND modules.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional multi-tenant storage systems are used, then system simplicity is maintained, but performance isolation among tenants cannot be achieved
Solution Approach 1:
The storage system is segmented into multiple NVM Sets, each associated with specific cores and submission queues. Each NVM Set is further divided into partitions that can be independently allocated to different tenants, enabling performance isolation through structural segmentation of the storage resource hierarchy.
Solution Approach 2:
The patent introduces a new dimension of isolation by associating NVM Sets with specific CPU cores and submission queues, creating a multi-dimensional isolation architecture that combines core-level, queue-level, and storage-level segmentation to achieve comprehensive tenant isolation.
2Reliability
If performance isolation mechanisms are implemented, then QoS guarantees are achieved, but host-side software overhead increases
Solution Approach 1:
The storage device autonomously manages QoS enforcement through internal arbitration mechanisms that operate independently of host software. The arbiter within the storage device automatically schedules I/O requests based on tenant priorities and QoS parameters without requiring host-side intervention, reducing host software overhead while maintaining QoS guarantees.
Solution Approach 2:
The patent introduces an arbiter as an intermediary component that sits between the submission queues and NVM Sets, automatically managing resource allocation and QoS enforcement. This intermediary handles the complexity of QoS management internally, shielding the host system from overhead while ensuring service level agreements are met.
3Reliability
If NVM Sets are associated with specific cores, then performance isolation is improved, but adaptability to different core allocations decreases
Solution Approach 1:
The association between NVM Sets and cores/submission queues is designed to be dynamic rather than static. The system can reconfigure which cores and submission queues are associated with which NVM Sets based on changing workload requirements and tenant needs, maintaining performance isolation while adapting to different core allocation scenarios.
Data Source
AI summary
A system is disclosed. The system may include a processor. The system may also include a first submission queue (SQ) and a second SQ. The first SQ may be associated with a first Quality of Service (QoS) level and the second SQ may be associated with a second QoS level, the first QoS level being different from the second QoS level. An application may be running on the processor and using a first namespace (NS). The processor may be configured to receive a first Non-Volatile Memory (NVM) Set create command to establish a first NVM Set associated with the first SQ. The processor may be further configured to receive a second NVM Set create command to establish a second NVM Set associated with the second SQ. The processor may be further configured to receive a first NS create command to establish a first NS associated with the first NVM Set. The processor may be further configured to receive a second NS create command to establish a second NS associated with the second NVM Set. The processor may be further configured to place an input/output (I/O) request sent from the application to at least one storage device in the first SQ based at least in part on the I/O request being associated with the first NS, the first NS being associated with the first NVM Set, and the first NVM Set being associated with the first SQ.