Non-volatile Memory Shielding Voltage Leakage Current
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Solution Overview
Problem
Non-volatile memory arrays face inaccuracies in reading stored data due to leakage currents that affect the evaluation of bit states, particularly in virtual ground arrays where currents from neighboring transistors interfere with the measurement of the selected transistor's current, leading to incorrect bit state evaluations.
Innovation Solution
A non-volatile memory package with a shielding voltage applicator that applies a voltage to downstream transistors to suppress leakage currents, ensuring that the bit sensor receives a more accurate read current by reducing interference from neighboring transistors, thereby improving the accuracy of bit state evaluation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a voltage is applied to read data from a selected transistor in a non-volatile memory array, then the cell current can be measured, but leakage current flows into neighboring downstream transistors causing measurement inaccuracy
Solution Approach 1:
The patent applies preliminary anti-action by preemptively counteracting the harmful leakage current effect. Before the leakage current can significantly distort the measurement, the system performs multiple read operations with different downstream transistor configurations (enabled/disabled states) and uses differential measurement to cancel out the leakage component. This preliminary counter-measurement approach eliminates the harmful effect rather than trying to prevent it entirely.
Solution Approach 2:
The patent implements feedback by using the measured read current to inform subsequent read operations. The system performs an initial read to characterize the leakage current magnitude, then uses this information to adjust subsequent measurements. The differential measurement process feeds back the leakage characterization into the final bit state determination, continuously refining the accuracy of bit state evaluation.
2Measurement precision
If multiple read operations are performed to compensate for leakage current, then measurement accuracy improves, but reading time increases
Solution Approach 1:
The patent applies periodic action by structuring the read operation as a sequence of discrete, repeated measurement cycles. Instead of continuous measurement, the system performs periodic read operations with alternating states of downstream transistors, capturing data at specific intervals. This periodic sampling approach efficiently characterizes the leakage current and enables accurate bit state determination through differential comparison, reducing total reading time compared to continuous compensation methods.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The shielding voltage applicator enhances the accuracy of reading stored data by minimizing leakage currents, allowing for reliable evaluation of bit states and reducing errors in multi-level transistors, which is particularly beneficial for virtual ground arrays.
Implementation Method 1
A shielding voltage applicator is adapted to apply a voltage to the input terminal or the output terminal of a downstream transistor of the plurality of transistors
Implementation Method 2
A read voltage supply is provided to supply a voltage to the input terminal of a selected transistor of the plurality of transistors, to induce a cell current between the input terminal and the output terminal of the selected transistor
Data Source
AI summary
A non-volatile memory package includes a non-volatile memory array having a plurality of transistors that are electrically coupled in series, each of the transistors having an input terminal and an output terminal such that the output terminal of one of the transistors is coupled to the input terminal of a next transistor in a downstream direction. A read voltage supply supplies a voltage to the input terminal of a selected transistor of the plurality of transistors, to induce a cell current between the input terminal and the output terminal of the selected transistor. A bit sensor receives and evaluates a read current from the output terminal of the selected transistor. A shielding voltage applicator applies a voltage to the input terminal or the output terminal of a downstream transistor of the plurality of transistors, the downstream transistor being in the downstream direction from the selected transistor.