Non-volatile Memory Source Line Resistance Compensation
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Solution Overview
Problem
Non-volatile memory devices face inefficiencies due to varying source line resistance across memory cells, leading to non-uniform program speed and cell program threshold voltage distribution, especially during programming operations.
Innovation Solution
A non-volatile memory device modifies the bit-line bias voltage based on the location of the memory cell relative to the nearest source line to compensate for source line resistance, ensuring uniform program speed and improved programming efficiency by adjusting the bit-line bias voltage to maintain consistent drain-to-source voltage across memory cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cells are arranged in a large array to increase storage capacity, then the source line resistance increases due to greater distance between source contact and memory cells, but this causes non-uniform program speed and cell program threshold voltage distribution
Solution Approach 1:
The patent applies local quality by providing different bit-line bias voltages to different columns of memory cells based on their specific location. Memory cells in columns farther from the source contact receive higher bit-line bias voltages to compensate for the increased source line resistance in those regions, while cells closer to the source contact receive lower voltages. This location-dependent voltage adjustment ensures uniform program threshold voltage distribution across the entire memory array despite variations in source line resistance.
2Quantity of substance
If the distance between source contact and memory cell increases to accommodate more cells, then storage capacity increases, but program efficiency decreases due to higher source line resistance
Solution Approach 1:
The patent employs parameter changes by dynamically adjusting the bit-line bias voltage parameter based on the column location of memory cells. The system modifies the electrical parameter (bit-line bias voltage) to compensate for the physical parameter变化 (source line resistance) that occurs with increased distance. This allows the memory array to maintain high program efficiency across all columns regardless of their distance from the source contact, enabling larger storage capacity without sacrificing programming speed.
3Device complexity
If a single bit-line bias voltage is applied to all memory cells, then device complexity is reduced, but program uniformity deteriorates due to varying source line resistance
Solution Approach 1:
The patent applies segmentation by dividing the memory array into multiple columns and assigning different bit-line bias voltages to each column based on its position relative to the source contact. This segmentation approach transforms the single uniform voltage control into multiple localized voltage zones, where each zone is optimized for its specific source line resistance characteristics. The segmentation enables precise control over program uniformity while managing device complexity through systematic voltage distribution.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution achieves more uniform program speed and improved program efficiency by compensating for source line resistance variations, allowing for consistent cell program threshold voltage distribution across the memory cell array.
Implementation Method 1
source line resistance associated with the memory cells increases. In particular, the source line resistance is a function of the distance between the source contact and memory cell selected for program
Data Source
AI summary
A non-volatile memory device determines the bit-line location of a memory cell selected for memory operation relative to a nearest source line, generates a modified bit-line bias voltage based on the bit-line location and applies the modified bit-line bias voltage to the selected memory cell. In some embodiments, the memory cell is selected to be programmed. In this manner, the non-volatile memory device compensates for source line resistance at the memory cells.