Non-Volatile Memory State Distribution Narrowing
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Solution Overview
Problem
Non-volatile memory systems face challenges in maintaining accurate data storage due to widening state distributions caused by charge traps between memory cells, especially as device sizes shrink, leading to reduced programming speed and endurance.
Innovation Solution
Incorporating a stress or pre-conditioning phase into the erase and programming operations, which involves applying differential voltage pulses to wordlines and bitlines to reduce charge traps, including a double-pulse pre-conditioning method that enhances the pre-conditioning field and reduces program noise.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If device sizes are shrunk to increase storage capacity, then storage density is improved, but state distribution widens due to charge traps
Solution Approach 1:
A stress phase is applied before the actual erase or programming operation to pre-condition the memory cells. This preliminary action reduces charge traps and narrows state distributions before data is written, ensuring tighter distributions even in scaled devices.
Solution Approach 2:
The stress phase applies voltages that counteract the formation of charge traps before they can degrade state distributions. By applying opposite or compensating stresses beforehand, the harmful effects of scaling are mitigated.
2Device complexity
If traditional erase and programming operations are used, then device simplicity is maintained, but state distributions widen reducing programming accuracy
Solution Approach 1:
The erase and programming operations are segmented into distinct phases: a stress phase followed by the actual erase/program phase. This segmentation allows the stress phase to prepare the cells by reducing charge traps, resulting in narrower state distributions without significantly increasing overall complexity.
Solution Approach 2:
The stress phase serves as a preliminary preparation step that modifies the electrical characteristics of memory cells before the main erase or programming operation, ensuring tighter state distributions and improved programming accuracy.
3Device complexity
If charge traps are not addressed, then device complexity remains low, but programming speed degrades due to distribution widening
Solution Approach 1:
The stress phase is inserted before programming to pre-condition memory cells by reducing charge traps. This preliminary action ensures that subsequent programming operations achieve tighter state distributions faster, improving effective programming speed without adding complex hardware.
Solution Approach 2:
The stress phase is applied periodically before erase and programming operations, creating a rhythm of preparation followed by data manipulation. This periodic pre-conditioning maintains consistent programming performance across multiple operations.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves the reliability and endurance of non-volatile memories by minimizing the effects of charge traps, reducing the number of failed bits over cycles, and maintaining programming speed without degrading performance.
Implementation Method 1
accurate storage of data is dependent upon the data being both written and read back with accuracy. The accurate programming of data relies upon the individual memory cells being written into well-defined distributions of threshold voltage values for each of the data states that the memory cells may store. This is particularly true of multistate devices, with the situation becoming ever more critical as device sizes shrink and the voltage window allotted for an increasing number of states becomes smaller.
Implementation Method 2
performing an erase operation on the memory cells of one or more selected erase blocks, where the erase operation includes performing a stress phase and an erase phase
Data Source
AI summary
Techniques are presented for use in memory devices to improve reliability and endurance by reducing the widening in state distributions, that occurs after multiple write/erase cycles. One set of techniques uses a pre-conditioning operation where a pulse series, which may include program and gentle erase, are applied to one or more wordlines while a voltage differential is applied in the wordline direction, bitline direction, or both. Another set of techniques uses a dual or multi-pulse program process, where an increased wordline-to-wordline differential used in the first pulse of a pair.