Non-Volatile Memory Controller Sub-Table Management
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Solution Overview
Problem
The management of logical-to-physical address mapping tables in non-volatile memory devices becomes inefficient as storage capacity increases, requiring effective methods to optimize the use of limited temporary storage space while handling frequent updates and read requests.
Innovation Solution
Implementing a memory controller that utilizes linked lists to manage sub mapping tables, allowing for flexible allocation of storage space by separating nodes into free, unsaved, and unchanged linked lists, and dynamically reassigning nodes based on usage frequency and storage capacity thresholds.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the logical-to-physical address mapping table is stored entirely in temporary storage, then data access speed is improved, but the device complexity and temporary storage requirements increase significantly
Solution Approach 1:
The logical-to-physical address mapping table is divided into multiple sub-mapping tables, each stored in separate memory blocks. Only the currently needed sub-mapping table is loaded into temporary storage (DRAM), reducing the temporary storage burden while maintaining fast access speeds for active mappings.
Solution Approach 2:
The mapping table is pre-divided into sub-mapping tables that can be independently loaded. When a logical address range is accessed, the corresponding sub-mapping table is pre-loaded into temporary storage, ensuring fast access is available when needed without requiring the entire mapping table in memory.
2Adaptability or versatility
If sub-mapping tables are frequently updated to reflect new logical-to-physical mappings, then data storage flexibility is improved, but the computational load and update time increase
Solution Approach 1:
The mapping table is segmented into sub-mapping tables that can be independently updated. When logical-to-physical mappings change, only the affected sub-mapping table needs to be updated rather than the entire mapping table, reducing computational load and update time.
Solution Approach 2:
Old sub-mapping table data is discarded and new data is loaded only when necessary. The system maintains a pool of sub-mapping tables in temporary storage, replacing them as needed based on access patterns, rather than continuously updating all mappings.
3Speed
If more sub-mapping tables are kept in temporary storage, then data access speed is improved, but the loss of substance (temporary storage space) increases
Solution Approach 1:
Different portions of the mapping table (sub-mapping tables) are loaded into temporary storage based on local access patterns. Frequently accessed logical address ranges have their sub-mapping tables resident in DRAM, while less frequently accessed ranges remain in non-volatile memory, optimizing the use of limited temporary storage space.
Data Source
AI summary
A high-performance data storage device is disclosed. A non-volatile memory stores a logical-to-physical address mapping table that maps logical addresses recognized by a host to a physical space in the non-volatile memory. The logical-to-physical address mapping table is divided into a plurality of sub mapping tables. A memory controller utilizes temporary storage when controlling the non-volatile memory. The memory controller plans a sub mapping table area in the temporary storage to store sub mapping tables corresponding to a plurality of nodes which are linked and managed by multiple linked lists.