NVM Test Cells Detect Subnormal Voltage to Abort Power Up
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Solution Overview
Problem
Conventional processing systems lack robust mechanisms to protect system configuration information stored in non-volatile memory from power attacks, where a subnormal read voltage can lead to incorrect reading of configuration bits, potentially causing severe damage to the system.
Innovation Solution
The implementation of test cells that share a common power supply with non-volatile memory, configured to output different values when a subnormal read voltage is applied, allowing for detection of power attacks by comparing output read values with pre-programmed values, and aborting the power-up process if a subnormal voltage is detected.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Duration of action of stationary object
If the system uses non-volatile memory to store configuration information, then the configuration information is retained when powered down, but the system becomes vulnerable to power attacks where subnormal read voltage causes incorrect reading of configuration bits
Solution Approach 1:
The patent applies preliminary action by performing a test read operation on the NVM before the actual configuration read operation. The test read uses a first read voltage to detect whether the NVM is susceptible to power attacks. Based on the test result, the system decides whether to proceed with the configuration read at a second read voltage, thereby preventing incorrect reading before it can occur.
Solution Approach 2:
The patent introduces an intermediary mechanism in the form of a test read operation that mediates between the power supply and the configuration read operation. This test operation acts as a gateway that verifies the safety of proceeding with the actual configuration read, preventing direct exposure to potential power attacks.
2Reliability
If the system performs test reads to detect power attacks, then the system protection against power attacks is improved, but the power-up time increases due to additional read operations
Solution Approach 1:
The patent applies partial action by performing only a test read operation on the NVM without fully executing the configuration read operation. The test read uses a first read voltage and checks whether the read value matches an expected value, allowing the system to detect power attacks without completing the full configuration read sequence, thus minimizing time loss while maintaining protection.
3Measurement precision
If the system reads configuration information at normal voltage, then correct reading is ensured, but the system cannot detect power attacks that use subnormal voltage
Solution Approach 1:
The patent applies parameter changes by varying the read voltage parameter between two different values: a first read voltage for the test operation and a second read voltage for the actual configuration read. By changing the voltage parameter and observing the effect on read values, the system can detect whether the NVM is susceptible to power attacks and adjust subsequent reading operations accordingly.
Data Source
AI summary
Systems and methods for detecting power attacks related to subnormal read voltage on an integrated circuit. Upon initiating power up of the integrated circuit and prior to reading configuration information from non-volatile memory (NVM), test cells associated with the NVM are read first. The test cells share a common power supply with the NVM and output read values from the test cells are configured to deviate from values pre-programmed in the test cells when a subnormal read voltage is applied on the common power supply. Thus, by comparing the output read values with the pre-programmed values, it can be determined whether voltage of the common power supply is subnormal, wherein configuration information will be read incorrectly at a subnormal read voltage. If the voltage is subnormal, power up is aborted. Otherwise, power up is allowed to proceed by reading the configuration information from the NVM.