Non-Volatile Memory Trimming via Parallel Word Line Testing
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Solution Overview
Problem
Conventional methods for determining optimum initial programming voltages in non-volatile memory devices require excessive erase/program cycling, leading to reduced device lifespan and high manufacturing costs due to the need for dedicated testers and multiple trials across word lines.
Innovation Solution
A method where a sample of word lines within a block are tested in parallel to derive a statistical average of starting programming voltages, reducing the number of block erasures and allowing all word lines to be erased together, thereby minimizing erase cycling and eliminating the need for expensive dedicated testers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional methods are used to determine optimum initial programming voltages by testing each word line individually with multiple erase/program cycles, then accurate voltage determination is achieved, but the number of erase cycles increases significantly reducing device lifespan
Solution Approach 1:
The patent combines multiple word lines into a single block for parallel testing. Instead of testing each word line individually with separate erase cycles, the method tests a sample of word lines within a block simultaneously, sharing the erase cycle resource and reducing the total number of erase operations required.
Solution Approach 2:
The patent performs preliminary testing on a sample of word lines within a block to determine their programming characteristics before full production. This preliminary action on a representative sample allows extrapolation to the entire block, avoiding exhaustive testing of every word line and significantly reducing erase cycles.
2Measurement precision
If dedicated testers are used to perform multiple trials for determining initial programming voltages, then accurate voltage values are obtained, but manufacturing costs increase
Solution Approach 1:
The patent enables the memory device to perform its own trimming operation using its internal circuitry and resources. The device can test and determine its own initial programming voltage characteristics without requiring external dedicated testers, thereby reducing manufacturing complexity and cost.
Solution Approach 2:
The patent makes the memory device itself multi-functional by enabling it to serve both as the object being tested and as the testing instrument. The same memory circuitry used for data storage is also utilized for determining programming voltage characteristics, eliminating the need for separate dedicated testing equipment.
3Measurement precision
If individual word lines are tested sequentially with multiple erase cycles, then precise voltage determination is achieved, but processing time increases
Solution Approach 1:
The patent merges the testing process for multiple word lines into a single parallel operation within a block. By combining the testing of sample word lines and sharing erase cycles across them, the total processing time is significantly reduced compared to sequential testing of individual word lines.
Data Source
AI summary
High performance non-volatile memory devices have the programming voltages trimmed for individual types of memory pages and word lines. A group of word lines within each erasable block of memory are tested successive program loops to minimize the problem of incurring excessive number of erase/program cycles. An optimum programming voltage for a given type of memory pages is derived from statistical results of a sample of similar of memory pages.