Non-Volatile Memory Verification Skipping
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Solution Overview
Problem
Current non-volatile memory devices face challenges in improving data input/output speed and reducing wear on memory cells, leading to potential data safety issues due to the high number of verification operations required during programming.
Innovation Solution
The proposed solution involves a memory system with a control circuit that performs incremental step pulse programming (ISPP) by applying program voltage to non-volatile memory cells in multiple loops, including verification operations for multiple target levels, and skipping verification for certain levels based on preset criteria, thereby optimizing the number of verification operations and reducing wear on memory cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If verification operations are performed for all target levels during programming, then data accuracy is improved, but programming speed deteriorates and memory cell wear increases
Solution Approach 1:
The patent applies partial verification by selectively performing verification operations only for certain target levels based on programming status and criteria, rather than verifying all target levels. This reduces the total number of verification operations while maintaining data accuracy for critical levels, thereby improving programming speed without completely sacrificing reliability
Solution Approach 2:
The patent dynamically changes verification parameters (which target levels to verify) based on programming status, memory cell characteristics, and preset criteria. This adaptive approach allows the system to adjust verification intensity to balance between data accuracy and programming speed for different programming scenarios
2Reliability
If verification operations are performed for all target levels during programming, then data accuracy is improved, but memory cell wear increases
Solution Approach 1:
By performing verification operations only for selected target levels rather than all levels, the patent reduces the frequency of read operations on memory cells. This partial verification approach maintains data accuracy for critical target levels while reducing overall memory cell stress and extending device lifetime
Solution Approach 2:
The patent treats verification operations as a resource that should be minimized. By using selective verification based on presets and programming status, it reduces the consumption of memory cell endurance resources while maintaining necessary data accuracy through intelligent sampling of target levels
3Productivity
If the number of verification operations is reduced, then programming speed is improved, but data integrity may deteriorate
Solution Approach 1:
The patent changes which target levels undergo verification based on programming status, memory cell characteristics, and preset criteria. This dynamic parameter adjustment ensures that critical target levels are verified to maintain data integrity, while non-critical levels are skipped to improve programming speed
Solution Approach 2:
The patent uses feedback from programming status and verification results to dynamically adjust which target levels require verification. This feedback mechanism ensures that data integrity is maintained by verifying target levels that are most critical for correct programming, while reducing verification on levels that are less critical
Data Source
AI summary
A memory device includes a cell group including a plurality of non-volatile memory cells capable of storing data and a control circuit configured to perform plural program loops for storing the data, each program loop including a program voltage application operation and a verification operation. During the respective program loop, the control circuit performs the verification operation for an N target level, an N−1 target level lower than the N target level, and an N+1 higher than the N target level, in response to the program voltage application operation for the N target level. When a quantity of non-volatile memory cells having threshold voltages over the N+1 target level satisfies a preset criterion, the control circuit skips a next verification for a target level lower than the N+1 target level, in response to a next program voltage application operation for the N+1 target level.