Non-Volatile Memory Cell Voltage Offset for Gate Oxide Variation
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Solution Overview
Problem
High-density non-volatile memory systems face challenges in maintaining stability and accuracy due to variations in gate oxide thickness, leading to fluctuations in electrical resistivity and performance inconsistencies, particularly in three-dimensional NAND-type memory structures.
Innovation Solution
A method and system that adjust read and verify biasing voltage levels based on the location of target memory cells within the memory structure, applying incremental offsets to compensate for variations in gate oxide thickness, thereby improving programming precision and durability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If high-density non-volatile memory structures are used to increase storage capacity, then storage density is improved, but variations in gate oxide thickness cause fluctuations in electrical resistivity and performance inconsistencies
Solution Approach 1:
The patent applies local quality by determining the location of target memory cells within the memory structure and applying different incremental offset values to read and verify biasing voltages based on their specific position. This allows each region of the memory structure to receive customized voltage compensation tailored to its local gate oxide thickness variations, thereby maintaining performance consistency across high-density storage structures.
Solution Approach 2:
The patent changes the voltage parameter dynamically by applying incremental offset values to the read and verify biasing voltages based on the location of memory cells. This parameter adjustment compensates for the fluctuations in electrical resistivity caused by gate oxide thickness variations, enabling reliable operation across high-density memory structures with non-uniform oxide layers.
2Device complexity
If uniform read and verify biasing voltages are applied to all memory cells, then device complexity is reduced, but programming precision and durability are compromised due to gate oxide thickness variations
Solution Approach 1:
The patent implements local quality by segmenting the memory structure into different location-based regions and applying location-specific incremental offset values to read and verify voltages. This segmented approach maintains manageable complexity while significantly improving programming precision by accounting for local gate oxide thickness variations in each memory cell region.
3Reliability
If location-based incremental offset voltages are applied to compensate for gate oxide thickness variations, then programming precision and reliability are improved, but voltage control complexity increases
Solution Approach 1:
The patent applies preliminary action by pre-determining the location of target memory cells within the memory structure before programming operations. This preliminary location identification enables the system to pre-calculate and apply the appropriate incremental offset values to read and verify voltages, thereby improving reliability while managing complexity through advance preparation rather than real-time adjustment.
Data Source
AI summary
A method for programming a target memory cell in a memory array of a non-volatile memory system, the method comprising defining a default read biasing voltage value and a default verify biasing voltage value for each program state of a target memory cell of a memory structure, determining a location of a target memory cell within the memory structure and, based upon the determined location of the target memory cell, applying a first incremental offset voltage to the default read biasing voltage value with respect to each program state, and applying a second incremental offset voltage to the default verify biasing voltage value with respect to each program state.