Non-Volatile Memory Reading Method Voltage Adjustment
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Non-volatile memory devices face challenges in maintaining a narrow threshold voltage distribution width while preventing charge loss during increasing erase/program operation cycles, as the growing pass voltage applied during read operations can lead to charge loss in the floating gate.
Innovation Solution
A reading method for non-volatile memory devices that applies a read voltage to a selected memory cell, a first pass voltage to an adjacent memory cell, and a second pass voltage to other memory cells, with the first pass voltage adjusted based on the program state and the number of cycles, to balance threshold voltage distribution and charge retention.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a high pass voltage is applied to the control gate of adjacent memory cells during read operation to improve threshold voltage distribution width, then the threshold voltage distribution width is improved, but charge loss in the selected memory cell increases
Solution Approach 1:
The patent applies different pass voltages to different groups of memory cells: a first pass voltage to adjacent memory cells and a second pass voltage to other memory cells. This local differentiation allows optimization of threshold voltage distribution for the selected cell while minimizing charge loss through selective voltage application to non-adjacent cells.
Solution Approach 2:
The patent dynamically adjusts the pass voltage levels based on the program state of the selected memory cell. As the cell transitions through different program states, the pass voltages are modified to maintain optimal balance between threshold voltage distribution and charge retention, preventing static charge loss issues.
2Manufacturing precision
If the pass voltage is increased to maintain narrow threshold voltage distribution width, then the threshold voltage distribution width is improved, but the vertical and horizontal electric fields increase causing charge loss
Solution Approach 1:
The patent applies different pass voltages to different groups of memory cells: a first pass voltage to adjacent memory cells and a second pass voltage to other memory cells. This local differentiation allows optimization of threshold voltage distribution for the selected cell while minimizing charge loss through selective voltage application to non-adjacent cells.
Solution Approach 2:
The patent changes the pass voltage parameters dynamically based on the program state of the selected memory cell. By adjusting voltage levels according to the cell's transition stage, the system maintains optimal electric field strength for threshold voltage distribution while preventing excessive charge loss.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method improves the threshold voltage distribution width and reduces charge loss across multiple program states, optimizing performance as the number of erase/program cycles increases.
Implementation Method 1
As there is the growing level of the pass voltage applied to the control gate of the memory cell adjacent to the selected memory cell during the read operation, which is shown in the Reference 1, the vertical and horizontal electric fields applied to the selected memory cell increases.
Implementation Method 2
a program operation and an erase operation are achieved by injecting or withdrawing electrons to or from a floating gate of a memory cell, through well-known Fowler-Nordheim (F-N) tunneling
Data Source
AI summary
A non-volatile memory device includes a first selection transistor, a second selection transistor, and a plurality of memory cells serially coupled between the first selection transistor and the second selection transistor. A reading method of the non-volatile memory device includes applying a read voltage to a gate of a selected memory cell; applying a first pass voltage to a gate of a memory cell adjacent to the selected memory cell, and applying a second pass voltage to gates of the other memory cells, wherein the selected memory cell is in one program state among first to Tth program states in a direction that threshold voltage is increased, where T is a natural number greater than 2, and the first pass voltage is decreased as the selected memory cell goes toward the Tth program state.