Non-Volatile Memory Wafer Testing Bypass Masking

The patent extracts and separates the testing process into two independent paths: one for successful bit lines that proceeds normally through masking and verification, and another for failed bit lines that bypasses the masking step entirely. This extraction allows the testing process to continue efficiently without being blocked by failures in individual bit lines, thereby reducing overall testing time while maintaining reliability through selective processing.

The testing methodology employs dynamic adaptability by adjusting the testing sequence based on real-time detection of failed bit lines. When a failure is detected, the system dynamically switches from the standard masked verification path to an unmasked direct verification path, allowing the testing process to flow continuously without rigid adherence to a fixed sequence, thus minimizing time loss.

The patent applies local quality by differentiating the verification process based on the specific conditions of each bit line. For bit lines that pass initial testing, the standard multi-step erase and verify process with masking is applied to ensure high precision. For bit lines that fail initial testing, a simplified unmasked verification process is applied, recognizing that these bit lines require different handling and would not benefit from the full precision protocol, thus maintaining overall productivity.

The methodology implements partial action by applying the full erase-verify-masking sequence only where necessary (for successful bit lines), while using a reduced verification approach for failed bit lines. This partial application of the complete precision process to only those bit lines that need it maximizes both manufacturing precision for critical cells and productivity overall by avoiding redundant operations on failed cells.