Non-Volatile Memory Wear Leveling via Hierarchical Data Migration
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Solution Overview
Problem
Non-volatile memories face challenges in wear leveling due to the absence of a flash translation layer (FTL) hardware, leading to inefficiencies in address mapping and increased performance and capacity issues, making traditional hardware and software mapping table methods unsuitable.
Innovation Solution
A method that logically divides the non-volatile memory into multiple levels of physical units, migrating data across these units based on predefined time cycles to distribute access evenly, thereby achieving wear leveling without the need for additional hardware or long-term memory occupation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional hardware mapping table method is used, then wear leveling can be achieved, but additional hardware overhead and cost are required which is not suitable for non-volatile memory without FTL hardware
Solution Approach 1:
The patent replaces the hardware-based FTL mapping table mechanism with a software-based address translation mechanism. The processor translates logical addresses to physical addresses using a mapping relationship stored in memory, eliminating the need for dedicated FTL hardware while maintaining wear leveling functionality through software-controlled data migration.
Solution Approach 2:
The non-volatile memory system performs wear leveling autonomously through software-based address translation and data migration. The processor automatically manages the mapping relationships and migrates data between physical units based on access patterns, without requiring external FTL hardware intervention.
2Reliability
If software mapping table method is used, then wear leveling can be implemented, but performance deteriorates due to inefficient table lookup and increased counting steps
Solution Approach 1:
The patent pre-establishes mapping relationships between logical and physical addresses in a data structure stored in memory. This preliminary configuration allows for efficient address translation during operations, avoiding the need for real-time table lookups and reducing performance impact while maintaining wear leveling through systematic data migration.
3Reliability
If software mapping table with address mapping is implemented, then wear leveling can be achieved, but available capacity is reduced due to occupation of valuable memory space
Solution Approach 1:
The patent implements address mapping and wear leveling information locally within the memory structure itself, utilizing memory regions that would otherwise be unused or less critical. This localized approach minimizes the impact on overall available capacity while maintaining the necessary mapping relationships for wear leveling operations.
Data Source
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AI summary
A wear leveling and access method and device for a non-volatile memory, and a storage medium. The method comprises: logically dividing a non-volatile memory into physical units of p levels, the non-volatile memory comprising a plurality of physical units of the first level, each physical unit of the p-1-th level comprising a plurality of physical units of the p-th level, and p being a positive integer greater than one (S 110); when a time period corresponding to the physical units of the q-th level arrives, replacing the data of each of the physical units of the q-th level with other physical units of the q-th level, q being any positive integer from one to p (S120).