NVM Wipe-Out Verification Using Single-Read State Detection

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Solution Overview

Problem

Existing non-volatile memory (NVM) implementations are vulnerable to attacks that disrupt the wipe-out process, making it difficult to ensure complete data destruction and verification.

Innovation Solution

A method is provided to securely wipe-out NVM contents by setting all cells to a single state using a high voltage program or erase operation, followed by a single read operation to verify the state of all cells, utilizing parallel or series architectures to ensure rapid verification.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a traditional wipe-out operation is performed on NVM, then the memory content is cleared, but the verification of complete wipe-out is time-consuming and vulnerable to attacks

Engineering Contradiction:
Improvewipe-out verification reliabilityVSAvoidverification time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent applies partial verification by selecting and verifying only a subset of memory cells (e.g., one cell per row or column) rather than verifying all cells. This partial action approach significantly reduces verification time while still providing sufficient reliability to detect wipe-out failures, as the probability of an attacker successfully disrupting all selected cells is extremely low.

Inventive Principle:
Principle #16Partial or excessive action

Solution Approach 2:

The patent implements rapid verification by skipping the traditional time-consuming exhaustive verification process. Instead, it performs a quick check on selected cells immediately after the wipe-out operation, rushing through the verification phase to minimize the time window during which an attacker could disrupt the process.

Inventive Principle:
Principle #21Skipping (Rushing through)

2Measurement precision

If a comprehensive verification of all memory cells is performed, then complete wipe-out can be confirmed, but the process becomes slow and extends the vulnerability window

Engineering Contradiction:
Improvewipe-out completeness verificationVSAvoidwipe-out operation speed
Core Design Contradiction:
Measurement precisionVSProductivity

Solution Approach 1:

The patent uses partial verification on selected memory cells rather than comprehensive verification of all cells. This maintains sufficient measurement precision to detect wipe-out failures while dramatically improving productivity by reducing the verification time and extending operational speed.

Inventive Principle:
Principle #16Partial or excessive action

3Reliability

If the wipe-out process is extended to ensure thorough verification, then data destruction confidence increases, but the opportunity for attacker disruption increases

Engineering Contradiction:
Improvedata destruction confidenceVSAvoidattacker disruption opportunity
Core Design Contradiction:
ReliabilityVSObject-affected harmful factors

Solution Approach 1:

The patent rushes through the verification process by immediately checking selected cells after wipe-out without extending the process. This reduces the time window for attacker disruption while maintaining reliability through strategic selection of verification cells that provide high confidence in data destruction.

Inventive Principle:
Principle #21Skipping (Rushing through)

Solution Approach 2:

The patent implements feedback by verifying selected cells immediately after the wipe-out operation and using the verification results to confirm successful data destruction. This rapid feedback loop increases reliability while minimizing the time attackers have to disrupt the process.

Inventive Principle:
Principle #23Feedback

Data Source

PatentUS12499953B2Wipe-out and verification of a non-volatile memory
Publication Date: 2025.12.16 NXP BV
  • US12499953B2 patent drawing
  • US12499953B2 patent drawing
  • US12499953B2 patent drawing

AI summary

A method is described for performing a wipe-out and verification of a plurality of non-volatile memory (NVM) cells. The method includes performing an operation to set all the plurality of NVM cells to a single state. The single state may be one of a conducing or non-conducting state depending on the NVM architecture. After the operation to set the cells to the single state is complete, the verification is performed. In the verification operation, all cells of the plurality of NVM cells are set to the single state by performing a single read operation on the plurality of NVM cells. Detection of one of a conducting or non-conducting path through the plurality of NVM cells is used to verify if all cells of the NVM array had their contents wiped out. A notification is provided in response to all cells not being set to the single known state.