Non-Volatile Memory Write Delay Difference for PUF Stability
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Solution Overview
Problem
State-of-the-art non-volatile memory (NVM) Physical Unclonable Functions (PUFs) face challenges with high area overhead and unstable bits, which affect reliability and entropy choice.
Innovation Solution
A method and system that utilize a non-volatile memory write delay difference to reset and write to two memory cells, detecting voltage drops to generate comparison flags and terminate write operations, reducing unstable bits and area overhead through a write-back operation and combined read-write scheme.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional non-volatile memory PUF is implemented, then chip identification and encryption key generation are achieved, but area overhead increases and unstable bits occur
Solution Approach 1:
The patent combines read and write operations into a single integrated circuit structure, where the same memory cells and control logic are used for both operations. This merging eliminates the need for separate read and write circuitry, thereby reducing area overhead while maintaining PUF functionality and stability
Solution Approach 2:
The memory cells are designed to serve multiple functions: they act as both PUF elements for generating encryption keys and as storage cells for data retention. The same physical structure performs both identification and data storage roles, reducing the overall area required compared to dedicated separate circuits
2Ease of manufacture
If write operation is performed on non-volatile memory cells, then data is stored, but write delay variation causes unstable bits
Solution Approach 1:
The patent incorporates feedback mechanisms where the completion status of write operations is monitored and used to control subsequent operations. The system detects whether write operations have completed successfully and uses this information to determine when to proceed with read operations or to retry writes, thereby eliminating unstable bits caused by premature reads
Solution Approach 2:
The system performs preliminary write operations and waits for their completion before proceeding with read operations. By ensuring writes are fully completed beforehand, the system prevents reading data that hasn't been properly programmed, thereby eliminating unstable bits
3Reliability
If separate read and write circuits are used, then operation reliability is improved, but area overhead increases
Solution Approach 1:
The patent merges read and write circuits into a single integrated structure that shares common components such as memory cells, bit lines, and control logic. This consolidation reduces the total area while maintaining the reliability benefits of dedicated read and write pathways through careful timing control
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach decreases unstable bits and area overhead, ensuring reliable operation and efficient entropy generation for PUFs by monitoring write success and maintaining complementary states in memory cells.
Implementation Method 1
physical unclonable function generated by non-volatile memory write delay difference
Implementation Method 2
detecting a voltage drop of each of the bit line and the bit line bar
Data Source
AI summary
A method for performing a physical unclonable function generated by a non-volatile memory write delay difference includes a resetting step, a writing step, a detecting step, a terminating step and a write-back operating step. The resetting step includes resetting two non-volatile memory cells controlled by a bit line and a bit line bar, respectively. The writing step includes performing a write operation on each of the two non-volatile memory cells. The detecting step includes detecting a voltage drop of each of the bit line and the bit line bar, and comparing the voltage drop and a predetermined voltage difference value to generate a comparison flag. The terminating step includes terminating the write operation on one of the two non-volatile memory cells according to the comparison flag. The write-back operating step includes performing a write-back operation on another of the two non-volatile memory cells.