NVM Write Throughput Control Circuit Interleaving
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Solution Overview
Problem
Non-volatile memory arrays face limitations in operating speed and programming time due to high write current requirements, which restrict the number of data bits that can be written in parallel, exceeding system specifications.
Innovation Solution
The method involves interleaving the write windows for consecutive data bits across a memory array, allowing each data bit to be written at different times, thereby reducing the maximum write current consumption and enabling more data bits to be written without exceeding system specifications, using a write throughput control circuit to manage the write current and timing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple data bits are written in parallel to increase operating speed, then productivity is improved, but write current consumption increases beyond system specifications
Solution Approach 1:
The patent divides the write operation into multiple time segments, writing different data bits at different times rather than simultaneously. This segmentation of the write process allows the system to maintain higher overall productivity by utilizing multiple write windows while keeping the instantaneous write current within system specifications for each individual write operation.
2Use of energy by moving object
If write current is reduced to meet system specifications, then energy consumption is improved, but the number of data bits that can be written in parallel decreases
Solution Approach 1:
The patent employs periodic write actions with interleaved write windows, where write operations are performed in a repeating cycle across multiple data bits. Each write operation uses controlled current within system specifications, but the periodic repetition across multiple cycles enables the system to write more data bits overall, thereby maintaining high productivity while adhering to current constraints.
3Use of energy by moving object
If data bits are written sequentially to reduce write current, then energy consumption is improved, but total programming time increases
Solution Approach 1:
The patent prepares multiple write operations in advance by setting up interleaved write windows for multiple data bits before execution. This preliminary arrangement allows the system to perform write operations in an optimized sequence where each operation uses controlled current, and the overall programming time is reduced by having multiple operations ready to execute in parallel time slots rather than strictly sequential execution.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the total write time and allows for a larger number of data bits to be written in parallel, achieving increased operating speed and efficiency within system power constraints.
Implementation Method 1
programming (e.g., writing data to) the NVM cell may be performed by transferring charge carriers (e.g., electrons, holes) from the substrate (e.g., the source and/or the drain) to the floating gate 108 by tunneling through the thin gate oxide layer
Implementation Method 2
transferring charge carriers (e.g., electrons, holes) from the substrate (e.g., the source and/or the drain) to the floating gate 108 by tunneling through the thin gate oxide layer
Data Source
AI summary
A structure and method for increasing the operating speed and reducing the overall programming time of a memory array are provided herein. The method and structure reduce the maximum write current consumption, for writing a plurality of data bits to a NVM array, by writing the data bits sharing an activated word line at different times (e.g., activating bit lines associated with an activated word line at different times). The write operation of respective data bits, which individually utilize only a fraction of the overall write window of the bits, are interleaved so that the maximum write current of respective bits are offset in time from the maximum write current of another bit, allowing a larger number of data bits to be written without exceeding system specifications (e.g., maximum current) and reducing overall memory write time.