Non-Volatile Memory Write Termination and Power Failure Handling
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Computer systems face limitations in performance due to the combination of volatile DRAM and magnetic storage disks, which require multiple servers and increased operating costs to meet performance demands, as DRAM offers high performance but limited capacity and high power consumption, while magnetic disks provide large capacity but poor data access performance.
Innovation Solution
Implementing non-volatile memory integrated circuits that offer low power consumption, high read and write performance, and the ability to persist data across power cycles, allowing them to augment or replace DRAM and storage disks in the storage subsystem, with a data communication protocol that optimizes access to non-volatile memory modules.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If DRAM is used for main memory, then high performance random access is achieved, but capacity is limited and power consumption is high
Solution Approach 1:
The system dynamically switches between DRAM and non-volatile memory based on workload requirements, using DRAM for high-performance operations and non-volatile memory for capacity-intensive operations, thereby optimizing the balance between speed and power consumption
Solution Approach 2:
Non-volatile memory is designed to serve multiple functions including main memory replacement, storage expansion, and cache memory, allowing a single memory type to address multiple performance and power consumption scenarios
2Quantity of substance
If magnetic storage disks are used for storage, then large capacity is achieved, but data access performance is poor
Solution Approach 1:
The storage system is segmented into multiple non-volatile memory devices organized in a hierarchical structure with memory controllers, allowing parallel access operations and improving overall data access speed while maintaining large capacity
Solution Approach 2:
A memory controller acts as an intermediary between the host system and non-volatile memory devices, managing data transfer operations and optimizing access patterns to achieve high-speed data access comparable to DRAM
3Productivity
If non-volatile memory is used to replace DRAM and magnetic disks, then capacity and I/O performance are enhanced, but write verification complexity increases
Solution Approach 1:
The system performs preliminary write operations to non-volatile memory followed by verification operations, using power capacitors to ensure complete write cycles even during power failures, thereby simplifying the verification process by guaranteeing write completion
Solution Approach 2:
The memory controller implements feedback mechanisms to monitor write operation status and verify data integrity in non-volatile memory, automatically retrying failed writes and notifying the host system only when verification is complete, thereby reducing perceived complexity
4Productivity
If multiple servers are deployed to meet performance demands, then performance requirements are satisfied, but operating costs increase
Solution Approach 1:
The patent combines DRAM-like performance and non-volatile memory-like capacity into a unified memory system, allowing a single server to deliver the performance of multiple servers by eliminating the need for separate high-performance and high-capacity storage subsystems
Data Source
AI summary
In one embodiment of the invention, a memory apparatus for improved write performance is disclosed. The memory apparatus includes a base printed circuit board (PCB) having an edge connector for plugging into a host server system; a card level power source to provide card level power during a power failure; a memory controller coupled to the card level power source and having one or more memory channels; and one or more non-volatile memory devices (NVMDs) coupled to the card level power source and organized to respectively couple to the memory channels controlled by the memory controller. Each memory controller provides queuing and scheduling of memory operations on a channel for each NVMD in the memory channels. Responsive to power failure, the memory controller receives card level power and changes the scheduling of memory operations to the NVMDs in each memory channel.