Nonvolatile Memory Card Power Failure Protection
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Solution Overview
Problem
Computer systems face limitations in performance due to the combination of volatile DRAM and magnetic storage disks, leading to high server counts and operating costs, as DRAM offers high performance but limited capacity and is power-intensive, while magnetic disks provide capacity but poor data access performance.
Innovation Solution
Implementing non-volatile memory integrated circuits that offer low power consumption, high read/write performance, and persistence across power cycles, along with a data communication protocol that optimizes access to these modules, allowing them to augment or replace DRAM and storage disks, and using a server memory card architecture with master and slave memory controllers for efficient data management.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If DRAM is used for high-performance random access, then data access speed is improved, but power consumption increases and data is lost on power failure
Solution Approach 1:
The patent implements a power failure detection mechanism that activates before complete power loss occurs. The system detects power failure conditions preliminarily and triggers data save operations to non-volatile memory, ensuring data integrity without requiring continuous high-power operation of DRAM.
Solution Approach 2:
The patent introduces non-volatile memory as an intermediary between DRAM and persistent storage. This intermediary layer allows the system to maintain fast access characteristics while reducing power consumption and preventing data loss, as data can be quickly transferred from DRAM to non-volatile memory when power failure is detected.
2Quantity of substance
If magnetic storage disks are used for large capacity storage, then storage capacity is improved, but data access performance deteriorates
Solution Approach 1:
The patent segments the storage system into multiple layers: DRAM for high-speed access, non-volatile memory for persistent storage, and magnetic disks for bulk capacity. This segmentation allows each layer to operate at its optimal performance level, with the non-volatile memory serving as a buffer that provides fast access to frequently used data while maintaining large effective capacity.
3Productivity
If multiple servers are deployed to meet performance demands, then system performance is improved, but operating costs increase
Solution Approach 1:
The patent implements a multi-functional memory system where non-volatile memory serves multiple purposes: it acts as fast persistent storage, a buffer between DRAM and disks, and a power failure protection mechanism. This universality allows a single server to handle workloads that previously required multiple servers, reducing operating costs while maintaining performance.
4Speed
If write operations are terminated early to improve performance, then write speed is improved, but data integrity may be compromised
Solution Approach 1:
The patent implements a feedback mechanism where the system continuously monitors power supply status and write operation completion status. When power failure is detected, the system receives feedback and automatically initiates data save operations to non-volatile memory, ensuring data integrity without requiring full completion of all write operations under normal conditions.
Data Source
AI summary
In one embodiment of the invention, a memory apparatus for improved write performance is disclosed. The memory apparatus includes a base printed circuit board (PCB) having an edge connector for plugging into a host server system; a card level power source to provide card level power during a power failure; a memory controller coupled to the card level power source and having one or more memory channels; and one or more non-volatile memory devices (NVMDs) coupled to the card level power source and organized to respectively couple to the memory channels controlled by the memory controller. Each memory controller provides queuing and scheduling of memory operations on a channel for each NVMD in the memory channels. Responsive to power failure, the memory controller receives card level power and changes the scheduling of memory operations to the NVMDs in each memory channel.