NVMe Address Engine for PRP/SGL Latency Reduction
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Solution Overview
Problem
NVMe controllers face significant performance issues when processing read commands for SGL data buffers due to the out-of-order nature of data transfer, leading to increased latency, especially for larger read commands, as they need to trace a link-list structure to acquire host buffer address information.
Innovation Solution
Implementing an address engine that assembles an address table representing the SGL linked list to reduce latency, allowing for parallel data retrieval and host transfer, without requiring modifications to other system components, by using a block table to manage logical blocks and address tables to represent the SGL buffer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the controller traces the SGL link-list structure to acquire host buffer address information for out-of-order data transfer, then data transfer flexibility is improved, but processing time increases significantly
Solution Approach 1:
The patent pre-generates an address table that maps logical block addresses to physical host buffer addresses before data transfer operations. This preliminary action eliminates the need to trace the SGL link-list structure during actual data transfer, reducing processing time while maintaining the ability to handle out-of-order transfers. The address table is constructed by traversing the SGL structure in advance and storing the address mappings for quick lookup.
2Stability of the object's composition
If read data are aggregated in the controller buffer before sending to the host in-order, then data ordering is maintained, but read latency increases significantly for larger read commands
Solution Approach 1:
The patent segments the data transfer process into independent parallel operations. Instead of aggregating all data in the controller buffer before transfer, it divides the read command into multiple logical block transfers that can proceed in parallel. The pre-generated address table enables each segment to be transferred directly to the appropriate host buffer location without waiting for other segments, maintaining data ordering through address mapping while reducing overall latency.
Solution Approach 2:
The patent introduces a new dimension of address mapping by creating an address table that decouples the logical block address space from the physical host buffer address space. This dimensional transformation allows out-of-order data retrieval from storage to be mapped to in-order delivery to the host without requiring sequential processing or buffer aggregation, effectively solving the latency problem while maintaining ordering guarantees.
Data Source
AI summary
Read latency for a read operation to a host implementing a PRP/SGL buffer is reduced by generating an address table representing the linked-list structure defining the PRP/SGL buffer. The address table may be generated concurrently with reading of data referenced by the read command from a NAND storage device. A block table for tracking status of LBAs referenced by IO commands may include a reference to the address table which is used to transfer LBAs to host memory as soon as the address table is complete and a block of data referenced by an LBA has been read from the NAND storage device.