NVMe SSD Address Space Partitioning via PCI Switch NTBs
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Solution Overview
Problem
Current computer systems face challenges in configuring NVMe devices for redundancy and scalability, particularly in managing address spaces and namespaces across multiple CPUs and non-transparent bridges (NTBs) to avoid memory address conflicts and ensure data availability in case of failures.
Innovation Solution
The implementation involves an SSD driver that identifies and partitions the address space and namespaces of NVMe devices across CPUs and NTBs, using PCI switches with NTBs to translate CPU memory addresses into drive addresses, enabling data redundancy and scalability by assigning queue pairs to multiple CPUs and NTBs, and maintaining mirrored copies of data across SSDs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple CPUs access NVMe SSDs through a PCI switch with NTBs, then data redundancy and scalability are improved, but address space conflicts and system complexity increase
Solution Approach 1:
The patent divides the NVMe device address space into multiple distinct partitions, with each partition assigned to specific NTBs and CPUs. This segmentation prevents address conflicts by ensuring that different CPU-NTB combinations access different address ranges, thereby enabling multiple CPUs to simultaneously access the NVMe device through the PCI switch without interference.
Solution Approach 2:
The PCI switch with NTBs acts as an intermediary between multiple CPUs and the NVMe SSD. The NTBs translate CPU memory addresses into drive addresses, mediating the address space conflict by providing a mapping layer that allows multiple CPUs to access the same NVMe device through different address paths without direct address conflicts.
2Adaptability or versatility
If address space is partitioned amongst multiple NTBs and CPUs, then scalability is improved, but configuration complexity increases
Solution Approach 1:
The address space is segmented into multiple partitions that can be independently assigned to different NTBs and CPUs. This segmentation enables scalability by allowing the system to accommodate additional CPUs and NTBs by allocating new address partitions without reconfiguring existing assignments, thereby reducing configuration complexity as the system grows.
Solution Approach 2:
The address space partitioning is performed in advance during system initialization, with predetermined address ranges assigned to specific NTBs and CPUs. This preliminary configuration establishes a stable framework that simplifies future expansions, as new components can be integrated by allocating address partitions from the pre-established scheme without disrupting existing configurations.
3Reliability
If namespaces are partitioned amongst multiple CPUs and NTBs, then data availability is improved, but system complexity increases
Solution Approach 1:
Namespaces within the NVMe device are divided into multiple partitions, with each namespace partition assigned to specific CPU-NTB combinations. This segmentation ensures data availability by distributing namespace access across multiple CPUs, so that if one CPU or NTB fails, other CPUs can still access their assigned namespace partitions through alternative paths.
Solution Approach 2:
Each CPU-NTB combination is assigned specific namespace partitions with localized access rights, creating distinct access patterns for different CPU groups. This local quality assignment simplifies namespace management by providing clear, defined access boundaries rather than requiring complex global namespace management, thereby reducing system complexity while maintaining data availability.
Data Source
AI summary
Configuring NVMe devices for redundancy and scaling includes: identifying, by a first SSD (‘Solid State Drive’) driver executing on a first CPU (‘Central Processing Unit’), address space of a first SSD coupled to the first CPU by a first PCI (‘Peripheral Component Interconnect’) switch, the first PCI switch including one or more non-transparent bridges (‘NTBs’); partitioning, by the first SSD driver, the address space of the first SSD amongst the NTBs of the first PCI switch and the first CPU, where each NTB is configured to translate CPU memory addresses received from a CPU into a drive address in the address space partitioned to the NTB; and partitioning, by the first SSD driver, a plurality of namespaces of the first SSD amongst the first CPU and the NTBs.