NVMe AER AEN for Memory Validation Latency

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Solution Overview

Problem

Current memory device validation environments rely heavily on debug hardware, which increases costs and implementation challenges due to the need for constant delays and dedicated hardware to deterministically trigger cross features, leading to inefficiencies and higher latency.

Innovation Solution

The use of Non-Volatile Memory Express (NVMe) asynchronous event request (AER) and NVMe asynchronous event notification (AEN) to initiate and monitor firmware events, eliminating the need for debug hardware and reducing latency by allowing cross features to overlap in time with the primary function.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If debug hardware is used to detect FW events and trigger cross features, then deterministic protocol CF can be achieved, but infrastructure cost and complexity increase

Engineering Contradiction:
Improvedeterministic protocol CFVSAvoiddebug HW infrastructure
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent extracts the cross feature triggering function from the dedicated debug hardware infrastructure and relocates it to the host system's existing NVMe driver. The driver receives AEN notifications from the DUT and autonomously determines when to trigger cross features, eliminating the need for separate debug HW while maintaining deterministic behavior.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The host system's NVMe driver, which already handles standard NVMe operations, is enhanced to also handle deterministic cross feature triggering. This multi-functional approach allows the same driver to serve both normal NVMe communication and validation testing purposes, eliminating the need for dedicated debug HW.

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Reliability

If dedicated debug HW is used to monitor FW events, then cross feature triggering is achieved, but latency increases due to constant delay

Engineering Contradiction:
Improvecross feature triggeringVSAvoidlatency
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent replaces the mechanical/debug hardware-based event detection and timing system with a software-based NVMe driver implementation. This substitution eliminates the physical hardware delays inherent in dedicated debug HW and enables faster, more responsive cross feature triggering through direct software coordination.

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

3Reliability

If debug hardware is required for validation, then deterministic CF triggering is possible, but validation cost increases

Engineering Contradiction:
Improvedeterministic CF triggeringVSAvoidvalidation infrastructure cost
Core Design Contradiction:
ReliabilityVSEase of manufacture

Solution Approach 1:

The host system's existing NVMe driver performs self-service by handling both normal NVMe operations and deterministic cross feature triggering without requiring external dedicated debug hardware. The driver uses its own resources to receive AEN notifications and trigger cross features, making the validation infrastructure self-sufficient and cost-effective.

Inventive Principle:
Principle #25Self-service

Data Source

PatentUS12045494B2AER and AEN for overlapping cross feature
Publication Date: 2024.07.23 SANDISK TECHNOLOGIES LLC
  • US12045494B2 patent drawing
  • US12045494B2 patent drawing
  • US12045494B2 patent drawing

AI summary

The present disclosure generally relates to validating memory devices. Rather than using debug hardware (HW) to consume, record, and decode firmware (FW) events, standard non-volatile memory express (NVMe) asynchronous event request (AER) and NVMe asynchronous event notification (AEN) is used. The NVMe AER results in initiating a particular function to be performed by a device under test (DUT) and triggering a cross feature (CF) that should at least partially overlap in time with the particular function. Using NVMe AER and AEN will eliminate the need for debug HW, reduce FW custom logic, and reduce latency.