Non-Volatile Memory Block Protection and Erasure Control

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Solution Overview

Problem

Conventional semiconductor devices with non-volatile memory face challenges in providing high data confidentiality protection while allowing efficient processing and execution of instruction codes, as existing protection methods either compromise processing speed or lead to data leakage due to complex protection settings and potential security vulnerabilities.

Innovation Solution

A semiconductor device with a non-volatile storage unit divided into blocks, featuring a protection information area that allows block-by-block access control, where data is erased block-by-block when protection is canceled, ensuring high confidentiality and enabling execution of instruction codes without compromising processing speed.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If protection is canceled by erasing all stored data, then data confidentiality is maintained, but processing speed decreases and time is lost

Engineering Contradiction:
Improvedata confidentialityVSAvoidprocessing speed
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent divides the non-volatile memory into multiple blocks, each with its own protection status. Instead of erasing all data when canceling protection, the system erases data block-by-block based on individual protection settings. This segmentation allows selective data erasure, maintaining security while reducing processing time and improving productivity.

Inventive Principle:
Principle #1Segmentation

2Adaptability or versatility

If protection is set block-by-block, then flexibility and precision are improved, but device complexity increases

Engineering Contradiction:
Improveprotection flexibilityVSAvoidprotection setting complexity
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The memory is divided into blocks with individual protection information areas, enabling block-by-block protection control. This segmentation provides flexible protection settings while maintaining a relatively simple overall structure, as each block operates independently with its own protection status.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The protection settings are made dynamic and adjustable at the block level. The control unit can selectively enable or disable protection for specific blocks based on operational requirements, allowing the system to adapt to different security needs without requiring complex reconfiguration of the entire memory structure.

Inventive Principle:
Principle #15Dynamics

3Ease of operation

If protection is canceled using specific signals or passwords, then ease of operation is improved, but security reliability deteriorates due to potential vulnerabilities

Engineering Contradiction:
Improveprotection cancellation easeVSAvoidsecurity reliability
Core Design Contradiction:
Ease of operationVSReliability

Solution Approach 1:

The system uses the existing CPU operation flow to automatically manage protection cancellation. When a block's protection is canceled, the control unit automatically erases data in that block as part of the normal operation sequence. This self-service approach eliminates the need for separate protection cancellation signals or passwords, maintaining ease of operation while improving security reliability by removing potential vulnerability points.

Inventive Principle:
Principle #25Self-service

Data Source

PatentUS8156280B2Data protection for non-volatile semiconductor memory using block protection
Publication Date: 2012.04.10 RENESAS ELECTRONICS CORP
  • US8156280B2 patent drawing
  • US8156280B2 patent drawing
  • US8156280B2 patent drawing

AI summary

Receiving a request for canceling setting, a control circuit erases data stored in a corresponding block, changes a value of a protection flag, and cancels protection setting. When an overall protection is set for any block, the control circuit prohibits access to all blocks, except when it is an operation mode for activating a memory program contained in the microcomputer. Further, control circuit permits an access to a block M only when partial protection is set, CPU is in the mode for activating a memory program contained in the microcomputer and the access is for reading an instruction code in accordance with an instruction fetch.