NVMe Bridge Unit Virtual Buffering for Latency Reduction

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Solution Overview

Problem

Conventional bridge units for managing communication between NVMe-oF host units and NVMe-SSD storage devices require excessive memory and power due to dedicated buffers, leading to high latency, large size, and unnecessary costs.

Innovation Solution

Implementing a virtual buffer system within the bridge unit to manage intermediate data, reducing memory requirements and power consumption by using a virtual data memory address corresponding to physical memory, and translating PCIe transactions into RDMA packets for efficient data transfer.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If dedicated buffers are used for managing data transfer between NVMe-oF host unit and NVMe-SSD storage devices, then communication reliability is improved, but memory requirements and power consumption increase

Engineering Contradiction:

Improvecommunication reliabilityVSAvoidmemory requirements

Core Design Contradiction:

ReliabilityVSQuantity of substance

Solution Approach 1:

The patent merges multiple dedicated buffers (submission queue buffer, completion queue buffer, read/write data buffer, in-capsule write data buffer) into a single unified buffer memory within the bridge unit. This consolidation maintains all necessary buffering functions while reducing total memory requirements and eliminating redundant buffer structures, directly resolving the contradiction between reliability and memory quantity.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The unified buffer memory is designed to perform multiple functions that were previously handled by separate dedicated buffers. It can dynamically allocate memory regions for submission queues, completion queues, read/write operations, and in-capsule data storage, making a single memory resource serve universal purposes while reducing overall memory consumption.

Inventive Principle:

Principle #6Universality (Multi-functionality)

2Reliability

If dedicated buffers are used for managing data transfer between NVMe-oF host unit and NVMe-SSD storage devices, then communication reliability is improved, but power consumption increases

Engineering Contradiction:

Improvecommunication reliabilityVSAvoidpower consumption

Core Design Contradiction:

ReliabilityVSUse of energy by stationary object

Solution Approach 1:

The patent consolidates multiple dedicated buffers into a single unified buffer memory, reducing the total number of memory components that consume power. This merging maintains communication reliability through proper memory management while decreasing the overall power consumption of the bridge unit's memory subsystem.

Inventive Principle:

Principle #5Merging (Combining)

3Productivity

If multiple dedicated buffers are used in bridge unit, then data transfer capability is improved, but device size and cost increase

Engineering Contradiction:

Improvedata transfer capabilityVSAvoiddevice size

Core Design Contradiction:

ProductivityVSArea of stationary object

Solution Approach 1:

The patent merges four separate dedicated buffers into one unified buffer memory structure within the bridge unit. This consolidation reduces the physical area required for buffer storage while maintaining full data transfer capability through efficient memory allocation and management strategies that provide all necessary buffering functions in a compact form.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The unified buffer memory serves multiple data transfer functions simultaneously, providing submission queue buffering, completion queue buffering, read/write data buffering, and in-capsule data buffering capabilities within a single memory resource, thereby maintaining productivity while reducing device size.

Inventive Principle:

Principle #6Universality (Multi-functionality)

4Adaptability or versatility

If conventional bridge unit architecture is used, then protocol translation capability is improved, but device complexity increases

Engineering Contradiction:

Improveprotocol translation capabilityVSAvoiddevice complexity

Core Design Contradiction:

Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent simplifies the bridge unit architecture by merging multiple dedicated buffer components into a single unified buffer memory. This reduction in the number of components decreases device complexity while the NVMeoF-NVMe sub-module maintains protocol translation capability between NVMe-oF and NVMe protocols, resolving the contradiction between adaptability and complexity.

Inventive Principle:

Principle #5Merging (Combining)

Data Source

PatentUS11409465B2Systems and methods for managing communication between NVMe-SSD storage device(s) and NVMe-of host unit

Publication Date: 2022.08.09 SAMSUNG ELECTRONICS CO LTD

AI summary

A system manages communication between a non-volatile memory express-over fabric (NVMe-oF) host unit and multiple non-volatile memory express-solid state drive (NVMe-SSD) storage devices via a bridge unit. The bridge unit may include sub-modules to control operations. The bridge unit may generate a virtual data memory address corresponding to a scattered gathered list address. The bridge unit may not require a data buffer to store intermediate data. The system may be configured to initiate a memory WRITE/READ transaction to access a virtual data memory corresponding to a physical memory in the bridge unit for performing a data WRITE/READ operation by an NVMe-SSD storage device.