NVMe Distributed Cache Error Detection and Recovery
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Solution Overview
Problem
Distributed storage systems in data centers face challenges with network errors and data loss due to unreliable networks, leading to significant performance issues and downtime, despite using Erasure Coding for fault-tolerance, which increases processing overhead.
Innovation Solution
Implementing in-kernel error detection and Erasure Coding (EC) processes within the NVMe nodes, utilizing smart NICs with their own processors to offload error detection, correction, and data recovery operations from the main processors, and dynamically adjusting EC ratios based on data access frequency and application usage to optimize resource utilization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If Erasure Coding is used for fault-tolerance, then storage overhead is reduced, but processing overhead increases
Solution Approach 1:
The patent segments data into data blocks and generates parity blocks through Erasure Coding, allowing distributed storage across multiple devices. This segmentation reduces storage overhead by enabling efficient reconstruction of lost data from parity blocks, while the processing overhead is managed through optimized encoding algorithms and distributed computation across multiple nodes.
Solution Approach 2:
The patent performs preliminary Erasure Coding operations to generate parity blocks before data is needed, and pre-establishes distributed storage arrangements. This preliminary action allows the system to handle data recovery more efficiently when errors occur, as the computational heavy lifting of encoding is already completed, reducing real-time processing overhead during error recovery scenarios.
2Reliability
If data is replicated for fault-tolerance, then reliability improves, but storage overhead increases
Solution Approach 1:
The patent changes the parameter of data redundancy from simple replication (100% overhead) to Erasure Coding with configurable ratios (e.g., 4:2, 8:4). By adjusting the encoding parameters, the system achieves the same fault-tolerance level with reduced storage overhead, as parity blocks contain compressed redundancy information that can reconstruct multiple lost data blocks.
3Reliability
If error detection and recovery operations are performed on main processors, then data integrity is maintained, but system performance decreases
Solution Approach 1:
The patent extracts error detection and recovery operations from the main processing path by implementing them in the kernel layer and utilizing smart NICs with dedicated processors. This extraction allows data integrity operations to be performed in parallel without blocking the main application processing flow, thereby maintaining data integrity while preserving system performance.
Solution Approach 2:
The patent introduces smart NICs with integrated processors as intermediaries between the network and the main system. These intermediaries handle error detection, correction, and recovery operations locally at the network interface, preventing these operations from becoming bottlenecks for the main processors and maintaining both data integrity and system performance.
4Reliability
If data traverses the full I/O and network stacks, then protocol compliance is ensured, but latency increases
Solution Approach 1:
The patent performs error detection and basic data validation operations in the kernel layer before data enters the full I/O and network stacks. This preliminary action ensures protocol compliance requirements are met early in the processing chain, allowing subsequent layers to operate more efficiently with pre-validated data, thereby reducing overall latency while maintaining protocol compliance.
Data Source
AI summary
A Non-Volatile Memory express (NVMe) node includes a memory used at least in part as a shared cache in a distributed cache. At least one processor of the NVMe node executes a kernel of an Operating System (OS). A request is received from another NVMe node to read data stored in the shared cache or to write data in the shared cache and an error detection operation is performed on the data for the request using the kernel. In another aspect, the kernel is used to perform Erasure Coding (EC) on data to be stored in the distributed cache. A network controller determines different EC ratios based at least in part on indications received from NVMe nodes of frequencies of access of different data and/or usage of the distributed cache by different applications. The network controller sends the determined EC ratios to the NVMe nodes.