NVMe Completion Entry Aggregation for PCIe Bus Efficiency
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Solution Overview
Problem
The NVMe system's current method of posting completion entries via partial cache line writes is inefficient, leading to unnecessary read-modify-write operations and inefficient data transfer over the PCIe bus due to small write requests.
Innovation Solution
Implementing a method in a nonvolatile storage device to aggregate completion entries based on predefined criteria, allowing for full cache line writes and optimizing data transfer by grouping multiple small write requests into a single larger request.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If completion entries are posted individually via partial cache line writes, then the host device can be notified of command completion promptly, but the host device must perform inefficient read-modify-write operations
Solution Approach 1:
The patent merges multiple completion entries into a single aggregated completion entry that fills a complete cache line. Instead of posting individual small completion entries that trigger read-modify-write operations, the system accumulates multiple completion entries and posts them together as a full cache line write, eliminating the inefficient read-modify-write cycle while maintaining completion notification functionality.
2Loss of information
If single small write requests are sent over the PCIe bus, then individual completion entries can be transmitted, but data transfer efficiency is considerably reduced
Solution Approach 1:
The patent combines multiple small completion entry write requests into a single larger write request that utilizes the full cache line size. This aggregation reduces the number of PCIe bus transactions required to transmit the same amount of completion information, thereby improving data transfer efficiency while ensuring all completion entries are transmitted without loss.
3Reliability
If multiple small write requests are sent to host memory, then individual completion entries can be posted, but the number of write operations increases unnecessarily
Solution Approach 1:
The patent aggregates multiple completion entries into a single write operation that fills a complete cache line. This approach reduces the number of write operations from multiple individual posts to a single aggregated post, simplifying the operation count while maintaining complete and accurate posting of all completion entries through the aggregation buffer mechanism.
Data Source
AI summary
Methods, systems, and computer readable media for aggregating completion entries in a nonvolatile storage device are disclosed. On method is implemented in a data storage device including a controller and a memory. The method includes receiving a request to post a completion entry that indicates an execution of a command by a data storage device and determining whether the completion entry is to be aggregated with one or more completion entries prior to being sent by the data storage device to a host device memory. The method further includes, in response to determining that the completion entry is to be aggregated, aggregating the completion entry with at least one other completion entry within an aggregation data store per predefined aggregation criteria and sending an aggregation of the completion entry and the at least one other completion entry to the host memory device in response to a trigger event.