Non-volatile Memory Intelligent Compute Task Distribution
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Solution Overview
Problem
Current non-volatile storage systems face performance limitations due to the need for transferring large data sets to hosts for compute tasks, leading to increased latency and inefficiencies, as they lack optimal distribution of compute tasks between memory controllers and integrated memory assemblies based on data transfer and computational resource needs.
Innovation Solution
A non-volatile storage system comprising a memory controller and integrated memory assemblies with separate compute resources, where a module intelligently assigns compute tasks based on anticipated data transfer, computational resource requirements, and available bandwidth, allowing tasks to be performed either by the memory controller or control dies within the storage system.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If compute tasks are performed in the storage system rather than at the host, then data transfer time is reduced, but performance latency still remains high
Solution Approach 1:
The storage system is segmented into multiple independent compute nodes distributed across different memory controllers and memory devices. Each node can independently execute compute tasks on local data, enabling parallel processing and reducing the sequential latency bottleneck. The system divides the compute workload across multiple segments rather than relying on a single centralized processor.
Solution Approach 2:
The patent introduces a new dimension of computation within the storage system itself, moving from traditional host-centric processing to storage-embedded processing. By embedding compute capabilities directly in the storage architecture, the system adds a spatial dimension where data processing occurs close to the data location, reducing the distance and time for data transfer while maintaining computational functionality.
2Productivity
If compute resources are added within the storage system, then compute capability is improved, but device complexity increases
Solution Approach 1:
The memory controllers and memory devices are designed with multi-functionality, serving both as storage components and as compute nodes. These universal components can execute compute tasks locally while maintaining their primary storage functions, eliminating the need for separate dedicated compute hardware and reducing overall system complexity despite adding compute capability.
Solution Approach 2:
The storage system components perform self-service by executing compute tasks autonomously without requiring constant host intervention. The distributed compute nodes can independently manage their own compute workloads, data access, and coordination, reducing the complexity of centralized control while maintaining high compute capability across the system.
3Productivity
If compute tasks are distributed across multiple nodes, then resource utilization is improved, but task assignment complexity increases
Solution Approach 1:
The system implements feedback mechanisms where compute nodes continuously report their availability, workload status, and performance metrics to the coordination layer. This feedback enables intelligent, adaptive task assignment that considers real-time conditions, optimizing resource utilization while simplifying the assignment process through automated, data-driven decision-making rather than complex manual orchestration.
Solution Approach 2:
An intermediary coordination layer is introduced between the host and distributed compute nodes, serving as a mediator that handles task assignment and workload distribution. This intermediary layer abstracts the complexity of distributed task management from the host and individual nodes, providing simplified interfaces for task submission while managing the underlying distributed resource allocation automatically.
Data Source
AI summary
A non-volatile storage system includes a memory controller and multiple integrated memory assemblies separate from and in communication with the memory controller. The integrated memory assemblies each comprises a memory die and a control die. The control die is connected (e.g., bonded) to the memory die. The memory controller and the control die include separate compute resources (e.g., each includes a processor). The storage system is configured to receive a request to perform a compute task and assign that compute task to any one or more of the memory controller and the integrated memory assemblies based on anticipated amount of data to be transferred to or from non-volatile memory for the compute task, computational resource need of the compute task, and/or available bandwidth of the memory controller and the control dies.