NVMe Controller Command Execution Priority Logic
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Solution Overview
Problem
Current memory systems with SSDs using NVMe struggle to control the execution order of commands effectively, leading to latency and suboptimal performance, especially when handling commands with different priority requirements, as they process in the order received rather than prioritizing based on set priorities.
Innovation Solution
A memory system with a controller that determines and controls the execution order of commands based on pre-set priorities for each logical area, ensuring that commands for higher-priority areas are executed first, thereby optimizing processing performance without increasing the load on the host apparatus.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If commands are processed in the order they are issued, then the processing order is simple and predictable, but commands requiring immediacy cannot be executed promptly even if they have high priority
Solution Approach 1:
The patent implements a dynamic command execution mechanism where the execution order is not fixed but can be adjusted based on priority levels. The controller dynamically reorders commands in the execution queue according to the priority of their target logical areas, allowing high-priority commands to jump ahead of lower-priority ones while maintaining overall system manageability
Solution Approach 2:
The patent segments the command execution process into priority-based queues or priority levels. Commands are divided into different execution groups based on the priority of their target logical areas, with separate handling for high-priority and low-priority commands, enabling differential processing without completely restructuring the execution control mechanism
2Reliability
If priority-based execution order control is implemented, then critical commands are processed promptly improving response performance, but the controller complexity increases
Solution Approach 1:
The patent applies local quality by assigning different priority levels to different logical areas within the storage system. Each logical area can have its own priority setting, allowing the controller to apply different execution strategies locally based on the specific requirements of each area, rather than using a uniform approach across the entire system
Solution Approach 2:
The patent changes the execution parameter from simple FIFO (first-in-first-out) ordering to priority-based ordering. The controller modifies the execution sequence parameter according to the priority values associated with each logical area, transforming the execution behavior without fundamentally changing the controller's basic architecture
3Ease of operation
If host apparatus controls command issuance order, then command execution order can be controlled, but the host apparatus load increases and processing latency occurs
Solution Approach 1:
The patent extracts the command execution order control function from the host apparatus and relocates it to the storage device controller. The host simply issues commands without worrying about execution ordering, while the controller independently manages the reordering based on priority, separating the control concerns and reducing host involvement in execution sequencing
4Adaptability or versatility
If multiple NS with different priorities are supported, then adaptive performance control is achieved, but the system cannot properly control execution order of multiple commands
Solution Approach 1:
The patent makes the command execution system dynamic by introducing priority-based reordering capability. The execution queue is no longer static but can be dynamically rearranged based on the priority of commands and their target logical areas, allowing the system to adapt to different performance requirements while maintaining efficient processing
Data Source
AI summary
A memory system includes: a non-volatile memory that includes a plurality of logical areas; and a controller that controls access to each logical area of the non-volatile memory. The controller includes an execution order control part that determines an execution order of a command received in accordance with a priority set in advance to a logical area specified by the command.