NVMe Controller Memory Manager CMB Capacity
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Solution Overview
Problem
Current NVMe storage devices with the controller memory buffer (CMB) feature provide high performance but have limited storage capacity, necessitating an improved solution to enhance capacity while maintaining performance.
Innovation Solution
The implementation of a controller memory manager that stores NVMe data structures in both non-volatile and volatile memory, utilizing SRAM as a cache for NVMe queues and classifying host write transactions to optimize storage within DRAM, SRAM, and non-volatile memory, thereby increasing the capacity of the CMB/PMR without requiring a larger ASIC area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If NVMe data structures are stored in controller memory buffer (CMB), then performance is improved, but storage capacity is limited
Solution Approach 1:
The patent segments the storage capacity by dividing CMB into multiple independently manageable instances, each capable of storing NVMe data structures. This segmentation allows the system to serve multiple virtualization contexts simultaneously, effectively increasing the usable storage capacity while maintaining the performance benefits of CMB for each instance.
Solution Approach 2:
The patent implements multi-functionality by enabling a single physical CMB resource to serve multiple virtualization instances through dynamic allocation and management. The controller memory manager enables the CMB to function as multiple independent buffers, allowing one physical resource to fulfill multiple roles and serve diverse storage needs simultaneously.
2Quantity of substance
If CMB size is increased to provide more storage capacity, then storage capacity is improved, but ASIC area increases
Solution Approach 1:
The patent applies dynamics by implementing flexible, dynamic allocation of CMB resources across multiple instances rather than dedicating fixed, static memory regions. The controller memory manager dynamically allocates and manages CMB instances based on runtime requirements, allowing the system to optimize memory usage and avoid the need for permanently allocated larger ASIC memory structures.
Solution Approach 2:
The patent changes the parameter of CMB instance count and size dynamically through software management rather than requiring fixed hardware configuration. By allowing the number and size of CMB instances to be adjusted via parameters and configuration rather than hardwired ASIC design, the system achieves increased storage capacity without proportionally increasing ASIC area.
Data Source
AI summary
Embodiments of the present disclosure generally relate to an NVMe storage device having a controller memory manager and a method of accessing an NVMe storage device having a controller memory manager. In one embodiment, a storage device comprises a non-volatile memory, a volatile memory, and a controller memory manager. The controller memory manager is operable to store one or more NVMe data structures within the non-volatile memory and the volatile memory.