NVMe Controller Direct Queue Storage via PCIe
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Solution Overview
Problem
The complexity of data processing in conventional storage systems using SSDs is hindered by the limitations of SATA and AHCI standards, which do not optimize the performance capabilities of SSDs, leading to bottlenecks in data processing.
Innovation Solution
A data processing method and system utilizing an NVMe controller that communicates with a host via a PCIe bus, allowing direct storage of submission queue entries in an I/O submission queue based on PCIe packet entrance information, eliminating the need for doorbell mechanisms and simplifying the data processing process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the host and NVMe controller use doorbell mechanism for notification, then communication between host and controller is established, but the data processing process becomes complex
Solution Approach 1:
The patent extracts and removes the doorbell mechanism from the NVMe data processing system. By eliminating this notification mechanism, the system achieves direct memory access without the complexity of doorbell-based interrupt handling, while maintaining communication reliability through the PCIe bus's inherent capabilities
2Adaptability or versatility
If SATA/AHCI standards are used for SSD communication, then compatibility with conventional storage systems is maintained, but SSD processing capability is limited
Solution Approach 1:
The patent changes the communication interface parameters from SATA/AHCI protocols to PCIe bus with NVMe protocol. This parameter change enables the system to leverage the full processing capability of SSDs while maintaining adaptability through standardized PCIe interface and NVMe protocol specifications
3Reliability
If multiple notification steps are used in data processing, then data operation requests are properly handled, but processing speed is reduced
Solution Approach 1:
The patent implements preliminary action by pre-configuring the PCIe bus and memory addresses for direct data access. The host and NVMe controller establish direct memory access paths in advance, eliminating the need for multiple notification steps during data processing, thereby improving speed while maintaining reliability
Data Source
AI summary
A data processing method and system, where the method includes: receiving, by a non-volatile memory express (NVMe) controller, a first Peripheral Component Interconnect express (PCIe) packet sent by a host, where a memory in the NVMe controller is provided with at least one input/output (I/O) submission queue, and the first PCIe packet includes entrance information of a target I/O submission queue and at least one submission queue entry (SQE); and storing the at least one SQE in the target I/O submission queue based on the entrance information of the target I/O submission queue. Therefore, an NVMe data processing process is simplified and less time-consuming, and data processing efficiency is improved.