NVMe/FC Submission Queue Bypassing Kernel Space

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Solution Overview

Problem

Large-scale distributed storage systems face performance issues due to latency associated with traversing the kernel stack when passing storage commands, which can impair business operations by increasing latency in data processing.

Innovation Solution

The system enables concurrent user space and kernel space access for storage commands through private, reserved I/O queues, allowing applications to bypass the kernel space for latency-sensitive operations like NVMe/FC commands, thereby reducing latency and improving data processing efficiency.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If storage commands traverse the kernel stack, then command processing can be centralized and controlled, but latency increases and data processing performance deteriorates

Engineering Contradiction:
Improvecommand processing controlVSAvoidlatency
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent segments I/O queue access into two distinct paths: traditional kernel space queues for controlled processing and private user space queues for low-latency access. This segmentation allows different command types to traverse different paths, resolving the contradiction between centralized control and latency sensitivity.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces private I/O queues as an intermediary mechanism between user space applications and storage controllers. These private queues act as a mediator that eliminates the kernel stack traversal for latency-sensitive operations while maintaining the ability to process commands efficiently.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Device complexity

If all storage commands go through kernel space, then centralized management is simplified, but data processing efficiency decreases due to increased latency

Engineering Contradiction:
Improvemanagement complexityVSAvoiddata processing efficiency
Core Design Contradiction:
Device complexityVSProductivity

Solution Approach 1:

The patent applies local quality by providing different access mechanisms for different command types: private queues for latency-sensitive commands and traditional kernel queues for commands requiring centralized management. This localized differentiation optimizes both management complexity and processing efficiency without requiring complete system redesign.

Inventive Principle:
Principle #3Local quality

3Loss of time

If private queues enable direct user space access, then latency is reduced, but queue management complexity increases

Engineering Contradiction:
Improveaccess latencyVSAvoidqueue management complexity
Core Design Contradiction:
Loss of timeVSDevice complexity

Solution Approach 1:

The patent implements multi-functionality by designing private I/O queues that can be shared across multiple user space applications while maintaining their low-latency characteristics. The queues serve multiple purposes: direct access path, concurrency control mechanism, and performance optimization tool, thereby managing complexity through functional consolidation.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS20230127976A1Queue utilization for optimized storage access
Publication Date: 2023.04.27 INC A CALIFORNIA
  • US20230127976A1 patent drawing
  • US20230127976A1 patent drawing
  • US20230127976A1 patent drawing

AI summary

A storage controller includes a processing device to send a Non-Volatile Memory Express over Fibre Channel (NVMe/FC) command to a submission queue without routing the NVMe/FC command through a kernel space, the submission queue being reserved for direct access by an initiator device to a user space of the storage controller.